| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 194 unsigned ShiftAmount;
336 return ShiftedImm.ShiftAmount;
670 unsigned Shift = ShiftedImm.ShiftAmount;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 820 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, VT);
822 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
823 ShiftAmount);
[all...] |
| LegalizeDAG.cpp | 388 SDValue ShiftAmount = DAG.getConstant(NumBits,
391 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
552 SDValue ShiftAmount = DAG.getConstant(NumBits,
554 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 649 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) {
656 if (ShiftAmount > 0) {
657 m = v % ShiftAmount;
658 v = v >> ShiftAmount;
691 // ShiftAmount = number of left-shifted bits in the Hexagon instruction.
692 int ShiftAmount = VT.getSizeInBits() / 16;
693 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) {
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 764 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
771 if (Opc == ISD::SRL && ShiftAmount) {
775 ShiftAmount -= 1;
778 while (ShiftAmount--)
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 205 unsigned &ShiftAmount);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | [all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | [all...] |
