| /external/llvm/lib/Linker/ |
| LinkModules.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenInstruction.cpp | 241 std::pair<unsigned,unsigned> SrcOp = Ops.ParseOperandName(SrcOpName, false);
242 if (SrcOp > DestOp) {
243 std::swap(SrcOp, DestOp);
247 unsigned FlatOpNo = Ops.getFlattenedOperandNumber(SrcOp);
|
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandCondsets.cpp | 149 MachineInstr *genTfrFor(MachineOperand &SrcOp, unsigned DstR,
670 /// Generate a conditional transfer, copying the value SrcOp to the
674 MachineInstr *HexagonExpandCondsets::genTfrFor(MachineOperand &SrcOp,
676 MachineInstr *MI = SrcOp.getParent();
687 unsigned Opc = getCondTfrOpcode(SrcOp, Cond);
691 .addOperand(SrcOp);
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | [all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| LoopVectorize.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| SIInstrInfo.cpp | 707 const MachineOperand &SrcOp = MI->getOperand(1);
709 assert(!SrcOp.isFPImm());
710 if (SrcOp.isImm()) {
711 APInt Imm(64, SrcOp.getImm());
719 assert(SrcOp.isReg());
721 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
724 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 128 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
[all...] |
