/art/test/427-bitwise/src/ |
Main.java | 173 expectEquals(6, $opt$Xor(5, 3)); 174 expectEquals(0, $opt$Xor(0, 0)); 175 expectEquals(3, $opt$Xor(0, 3)); 176 expectEquals(3, $opt$Xor(3, 0)); 177 expectEquals(-4, $opt$Xor(1, -3)); 178 expectEquals(9, $opt$Xor(-12, -3)); 192 expectEquals(6L, $opt$Xor(5L, 3L)); 193 expectEquals(0L, $opt$Xor(0L, 0L)); 194 expectEquals(3L, $opt$Xor(0L, 3L)); 195 expectEquals(3L, $opt$Xor(3L, 0L)) [all...] |
/external/llvm/lib/IR/ |
Instruction.cpp | 212 case Xor: return "xor"; 466 /// In LLVM, the Add, Mul, And, Or, and Xor operators are associative. 469 return Opcode == And || Opcode == Or || Opcode == Xor || 502 case Xor: 526 /// In LLVM, the Xor operator is nilpotent. 529 return Opcode == Xor;
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/cts/tests/tests/renderscript/src/android/renderscript/cts/ |
AtomicTest.rs | 50 TEST_OP(Xor)
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/external/llvm/lib/Target/SystemZ/ |
SystemZTargetTransformInfo.cpp | 128 case Instruction::Xor:
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/external/llvm/lib/Transforms/Scalar/ |
LowerAtomic.cpp | 71 case AtomicRMWInst::Xor:
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BDCE.cpp | 234 case Instruction::Xor:
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LoopRotation.cpp | 231 case Instruction::Xor:
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/external/v8/src/compiler/ |
machine-operator.h | 155 V(Word, Xor) \
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/prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/gdiplus/ |
gdiplusheaders.h | 553 Status Xor(const RectF& rect); 554 Status Xor(const Rect& rect); 555 Status Xor(const Region *region); 556 Status Xor(const GraphicsPath *path);
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gdiplusimpl.h | [all...] |
/external/llvm/include/llvm/MC/ |
MCExpr.h | 418 Xor ///< Bitwise exclusive or. 504 return Create(Xor, LHS, RHS, Ctx);
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/external/clang/include/clang/AST/ |
StmtVisitor.h | 128 BINOP_FALLBACK(And) BINOP_FALLBACK(Xor) BINOP_FALLBACK(Or)
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/external/llvm/lib/Target/XCore/ |
XCoreLowerThreadLocal.cpp | 103 case Instruction::Xor:
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/external/llvm/lib/Transforms/InstCombine/ |
InstCombineShifts.cpp | 112 case Instruction::Xor: 210 case Instruction::Xor: 423 case Instruction::Xor: { 501 bool isValid = true; // Valid only for And, Or, Xor 510 case Instruction::Xor: [all...] |
InstCombineSimplifyDemanded.cpp | 220 } else if (I->getOpcode() == Instruction::Xor) { 334 case Instruction::Xor: { 356 // These bits cannot contribute to the result of the 'xor'. 387 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1. 392 // are flipping are known to be set, then the xor is just resetting those 393 // bits to zero. We can just knock out bits from the 'and' and the 'xor', 628 // Turn this into a xor if LHS is 2^n-1 and the remaining bits are known 633 Instruction *Xor = BinaryOperator::CreateXor(I->getOperand(1), C0); 634 return InsertNewInstWith(Xor, *I); [all...] |
InstCombineAndOrXor.cpp | 115 Op != Instruction::Xor) 149 else //if (Op == Instruction::Xor) 170 case Instruction::Xor: 202 // Adding a one to a single bit bit-field should be turned into an XOR 218 // the XOR is to toggle the bit. If it is clear, then the ADD has 224 // Pull the XOR out of the AND. 401 case Instruction::Xor: [all...] |
InstCombineVectorOps.cpp | 627 case Instruction::Xor: 690 case Instruction::Xor: { 790 case Instruction::Xor: [all...] |
/external/v8/src/ic/mips/ |
stub-cache-mips.cc | 139 __ Xor(scratch, scratch, Operand((flags >> kCacheIndexShift) & mask));
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/external/v8/src/ic/mips64/ |
stub-cache-mips64.cc | 140 __ Xor(scratch, scratch, Operand((flags >> kCacheIndexShift) & mask));
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/external/llvm/lib/CodeGen/ |
AtomicExpandPass.cpp | 266 case AtomicRMWInst::Xor: 547 case AtomicRMWInst::Xor:
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/external/llvm/lib/MC/ |
MCExpr.cpp | 108 case MCBinaryExpr::Xor: OS << '^'; break; 734 case MCBinaryExpr::Xor: Result = LHS ^ RHS; break;
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/external/llvm/include/llvm/ADT/ |
APSInt.h | 245 APSInt LLVM_ATTRIBUTE_UNUSED_RESULT Xor(const APSInt& RHS) const {
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/external/llvm/lib/Target/PowerPC/ |
PPCTargetTransformInfo.cpp | 130 case Instruction::Xor:
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/external/lldb/source/Expression/ |
IRInterpreter.cpp | 522 case Instruction::Xor: 629 case Instruction::Xor: 713 case Instruction::Xor: [all...] |
/external/llvm/lib/Analysis/ |
CostModel.cpp | 413 case Instruction::Xor: {
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