| /external/v8/src/x64/ |
| codegen-x64.h | 57 Register base_reg,
62 : base_reg_(base_reg),
70 Register base_reg,
75 : base_reg_(base_reg),
83 Register base_reg,
88 : base_reg_(base_reg),
|
| disasm-x64.cc | 340 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } function in class:disasm::DisassemblerX64
[all...] |
| macro-assembler-x64.cc | 739 Register base_reg = r15; local
740 Move(base_reg, next_address);
741 movp(prev_next_address_reg, Operand(base_reg, kNextOffset));
742 movp(prev_limit_reg, Operand(base_reg, kLimitOffset));
743 addl(Operand(base_reg, kLevelOffset), Immediate(1));
790 subl(Operand(base_reg, kLevelOffset), Immediate(1));
791 movp(Operand(base_reg, kNextOffset), prev_next_address_reg);
792 cmpp(prev_limit_reg, Operand(base_reg, kLimitOffset));
853 movp(Operand(base_reg, kLimitOffset), prev_limit_reg);
[all...] |
| assembler-x64.cc | 158 int base_reg = (has_sib ? operand.buf_[1] : modrm) & 0x07;
161 bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base.
181 } else if (disp_value != 0 || (base_reg == 0x05)) {
[all...] |
| /external/lldb/include/lldb/Core/ |
| EmulateInstruction.h | 190 RegisterInfo base_reg; // base register number member in struct:lldb_private::EmulateInstruction::Context::__anon14185::RegisterPlusIndirectOffset
197 RegisterInfo base_reg; // base register for address calculation member in struct:lldb_private::EmulateInstruction::Context::__anon14185::RegisterToRegisterPlusOffset
203 RegisterInfo base_reg; // base register for address calculation member in struct:lldb_private::EmulateInstruction::Context::__anon14185::RegisterToRegisterPlusIndirectOffset
246 SetRegisterPlusOffset (RegisterInfo base_reg,
250 info.RegisterPlusOffset.reg = base_reg;
255 SetRegisterPlusIndirectOffset (RegisterInfo base_reg,
259 info.RegisterPlusIndirectOffset.base_reg = base_reg;
265 RegisterInfo base_reg,
270 info.RegisterToRegisterPlusOffset.base_reg = base_reg
[all...] |
| /external/mesa3d/src/mesa/program/ |
| register_allocate.h | 44 unsigned int base_reg, unsigned int reg);
|
| register_allocate.c | 210 * Adds a conflict between base_reg and reg, and also between reg and
211 * anything that base_reg conflicts with.
219 unsigned int base_reg, unsigned int reg)
223 ra_add_reg_conflict(regs, reg, base_reg);
225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) {
226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]);
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_reg_allocate.cpp | 131 for (int base_reg = j;
132 base_reg < j + class_sizes[i];
133 base_reg++) {
134 ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
|
| brw_fs_reg_allocate.cpp | 119 for (int base_reg = j;
120 base_reg < j + class_sizes[i];
121 base_reg++) {
122 ra_add_transitive_reg_conflict(brw->wm.regs, base_reg, reg);
|
| brw_blorp_blit.cpp | 493 void alloc_push_const_regs(int base_reg);
743 brw_blorp_blit_program::alloc_push_const_regs(int base_reg)
748 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
[all...] |
| brw_wm_emit.c | [all...] |
| /external/lldb/source/Plugins/Instruction/ARM/ |
| EmulateInstructionARM.cpp | 3964 RegisterInfo base_reg; local
4097 RegisterInfo base_reg; local
4222 RegisterInfo base_reg; local
4373 RegisterInfo base_reg; local
4498 RegisterInfo base_reg; local
4687 RegisterInfo base_reg; local
4887 RegisterInfo base_reg; local
5017 RegisterInfo base_reg; local
5185 RegisterInfo base_reg; local
5200 RegisterInfo base_reg; local
5855 RegisterInfo base_reg; local
6062 RegisterInfo base_reg; local
6235 RegisterInfo base_reg; local
6473 RegisterInfo base_reg; local
6611 RegisterInfo base_reg; local
6725 RegisterInfo base_reg; local
6892 RegisterInfo base_reg; local
7053 RegisterInfo base_reg; local
7152 RegisterInfo base_reg; local
7299 RegisterInfo base_reg; local
7450 RegisterInfo base_reg; local
7564 RegisterInfo base_reg; local
7728 RegisterInfo base_reg; local
8207 RegisterInfo base_reg; local
9822 RegisterInfo base_reg; local
10022 RegisterInfo base_reg; local
10170 RegisterInfo base_reg; local
10422 RegisterInfo base_reg; local
10551 RegisterInfo base_reg; local
10720 RegisterInfo base_reg; local
10913 RegisterInfo base_reg; local
11067 RegisterInfo base_reg; local
11205 RegisterInfo base_reg; local
11376 RegisterInfo base_reg; local
11548 RegisterInfo base_reg; local
11715 RegisterInfo base_reg; local
11887 RegisterInfo base_reg; local
12013 RegisterInfo base_reg; local
[all...] |
| /external/lldb/source/Core/ |
| EmulateInstruction.cpp | 516 info.RegisterPlusIndirectOffset.base_reg.name,
524 info.RegisterToRegisterPlusOffset.base_reg.name,
533 info.RegisterToRegisterPlusIndirectOffset.base_reg.name,
|
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_state_init.c | 423 uint32_t base_reg; local
435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
[all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 1318 int base_reg = ((lir->opcode == kThumb2LdrdPcRel8) || local
[all...] |
| /art/compiler/dex/quick/arm64/ |
| codegen_arm64.h | 85 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
|
| int_arm64.cc | 301 RegStorage base_reg, int offset, int check_value,
309 Load32Disp(base_reg, offset, temp_reg);
[all...] |
| /art/compiler/dex/quick/x86/ |
| utility_x86.cc | [all...] |
| codegen_x86.h | [all...] |
| /art/compiler/dex/quick/ |
| codegen_util.cc | [all...] |
| mir_to_lir.h | [all...] |
| /art/compiler/dex/ |
| local_value_numbering.cc | 1333 int base_reg = (opcode == Instruction::IPUT_WIDE) ? 2 : 1; local
[all...] |
