| /external/valgrind/none/tests/mips32/ |
| branches.stdout.exp | 263 BGEZALL
264 bgezall :: 1, RSval: 0
265 bgezall :: 2, RSval: 1
266 bgezall :: 11, RSval: -1
267 bgezall :: 12, RSval: -1
268 bgezall :: 13, RSval: -2
269 bgezall :: 14, RSval: -1
270 bgezall :: 7, RSval: 5
271 bgezall :: 16, RSval: -3
272 bgezall :: 9, RSval: 12
[all...] |
| /external/valgrind/none/tests/mips64/ |
| branches.stdout.exp | 263 --- BGEZALL --- if RSval >= 0 then out = RDval + 4 else out = RDval + 6
264 bgezall :: out: 4, RDval: 0, RSval: 0
265 bgezall :: out: 5, RDval: 1, RSval: 1
266 bgezall :: out: 8, RDval: 2, RSval: -1
267 bgezall :: out: 9, RDval: 3, RSval: -1
268 bgezall :: out: 10, RDval: 4, RSval: -2
269 bgezall :: out: 11, RDval: 5, RSval: -1
270 bgezall :: out: 10, RDval: 6, RSval: 5
271 bgezall :: out: 13, RDval: 7, RSval: -3
272 bgezall :: out: 12, RDval: 8, RSval: 12
[all...] |
| /external/llvm/test/MC/Mips/ |
| mips-jump-delay-slots.s | 92 # CHECK: bgezall $6, 1332
94 bgezall $6,1332
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips2.s | 19 bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips2.s | 16 bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips2.s | 13 bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| valid.s | 32 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
|
| /external/llvm/test/MC/Mips/mips32/ |
| valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
|
| /external/v8/src/mips/ |
| assembler-mips.h | 658 void bgezall(Register rs, int16_t offset);
659 void bgezall(Register rs, Label* L) { function in class:v8::internal::Assembler
660 bgezall(rs, branch_offset(L, false)>>2);
[all...] |
| assembler-mips.cc | 1328 void Assembler::bgezall(Register rs, int16_t offset) { function in class:v8::Assembler
[all...] |
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 32 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 36 bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
|
| /external/v8/src/mips64/ |
| assembler-mips64.h | 649 void bgezall(Register rs, int16_t offset);
650 void bgezall(Register rs, Label* L) { function in class:v8::internal::Assembler
651 bgezall(rs, branch_offset(L, false)>>2);
[all...] |
| assembler-mips64.cc | 1307 void Assembler::bgezall(Register rs, int16_t offset) { function in class:v8::Assembler
[all...] |
