| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 377 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass);
380 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_YRegClass);
383 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass);
386 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_WRegClass);
|
| SIFixSGPRCopies.cpp | 233 MRI.constrainRegClass(Op.getReg(), RC);
239 MRI.constrainRegClass(Reg, &AMDGPU::VGPR_32RegClass);
|
| /external/llvm/lib/CodeGen/ |
| OptimizePHIs.cpp | 171 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
|
| UnreachableBlockElim.cpp | 194 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
|
| MachineCSE.cpp | 156 if (!MRI->constrainRegClass(SrcReg, RC))
571 if (!MRI->constrainRegClass(NewReg, OldRC)) {
|
| MachineRegisterInfo.cpp | 47 MachineRegisterInfo::constrainRegClass(unsigned Reg,
|
| TailDuplication.cpp | 300 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
452 MRI->constrainRegClass(VI->second, MRI->getRegClass(Reg));
[all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| PeepholeOptimizer.cpp | 440 MRI->constrainRegClass(DstReg, DstRC);
[all...] |
| MachineBasicBlock.cpp | 360 if (!MRI.constrainRegClass(VirtReg, RC))
[all...] |
| MachineLICM.cpp | [all...] |
| RegisterCoalescer.cpp | 701 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 453 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);
459 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass);
499 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) {
503 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) {
507 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) {
510 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) {
538 MRI.constrainRegClass(TrueReg, RC);
539 MRI.constrainRegClass(FalseReg, RC);
736 !MRI->constrainRegClass(Reg, OpRegCstraints))
[all...] |
| AArch64ConditionalCompares.cpp | 604 MRI->constrainRegClass(HeadCond[2].getReg(),
651 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),
654 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
|
| AArch64RegisterInfo.cpp | 343 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 154 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
195 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
|
| A15SDOptimizer.cpp | 669 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
|
| ARMBaseRegisterInfo.cpp | 583 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
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| ARMLoadStoreOptimizer.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineRegisterInfo.h | 534 /// constrainRegClass(ToReg, getRegClass(FromReg))
588 /// constrainRegClass - Constrain the register class of the specified virtual
595 const TargetRegisterClass *constrainRegClass(unsigned Reg,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 336 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
448 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
[all...] |
| FastISel.cpp | [all...] |
| SelectionDAGISel.cpp | 579 MRI.constrainRegClass(To, MRI.getRegClass(From));
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 701 MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
702 MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
[all...] |
