| /art/runtime/arch/arm/ |
| context_arm.cc | 44 uint32_t core_regs = frame_info.CoreSpillMask(); local
45 DCHECK_EQ(0u, core_regs & (static_cast<uint32_t>(-1) << kNumberOfCoreRegisters));
46 for (uint32_t core_reg : HighToLowBits(core_regs)) {
|
| /art/runtime/arch/x86/ |
| context_x86.cc | 43 uint32_t core_regs = local
45 DCHECK_EQ(1, POPCOUNT(frame_info.CoreSpillMask() & ~core_regs)); // Return address spill.
46 for (uint32_t core_reg : HighToLowBits(core_regs)) {
|
| /art/runtime/arch/x86_64/ |
| context_x86_64.cc | 43 uint32_t core_regs = local
45 DCHECK_EQ(1, POPCOUNT(frame_info.CoreSpillMask() & ~core_regs)); // Return address spill.
46 for (uint32_t core_reg : HighToLowBits(core_regs)) {
|
| /art/compiler/dex/quick/ |
| ralloc_util.cc | 63 const ArrayRef<const RegStorage>& core_regs,
82 core_regs_.reserve(core_regs.size());
83 for (const RegStorage& reg : core_regs) {
1376 RefCounts *core_regs = arena_->AllocArray<RefCounts>(core_reg_count_size, kArenaAllocRegAlloc); local
[all...] |
| mir_to_lir.h | 423 const ArrayRef<const RegStorage>& core_regs,
[all...] |
| /art/compiler/dex/quick/arm/ |
| target_arm.cc | 64 static constexpr ArrayRef<const RegStorage> core_regs(core_regs_arr);
597 reg_pool_.reset(new (arena_) RegisterPool(this, arena_, core_regs, empty_pool /* core64 */,
[all...] |
| /art/compiler/dex/quick/arm64/ |
| target_arm64.cc | 76 static constexpr ArrayRef<const RegStorage> core_regs(core_regs_arr);
625 reg_pool_.reset(new (arena_) RegisterPool(this, arena_, core_regs, core64_regs, sp_regs, dp_regs,
|
| /hardware/intel/img/psb_video/src/ |
| tng_enc_trace.c | 1046 static struct RegisterInfomation core_regs[] = { variable in typeref:struct:RegisterInfomation
[all...] |
