| /art/runtime/quick/ |
| quick_method_frame_info.h | 30 core_spill_mask_(0u),
37 core_spill_mask_(core_spill_mask),
46 return core_spill_mask_;
55 uint32_t core_spill_mask_; variable
|
| /art/compiler/dex/quick/arm/ |
| call_arm.cc | 416 if (core_spill_mask_ != 0u) {
417 if ((core_spill_mask_ & ~(0xffu | (1u << rs_rARM_LR.GetRegNum()))) == 0u) {
421 (core_spill_mask_ & ~(1u << rs_rARM_LR.GetRegNum())) |
422 ((core_spill_mask_ & (1u << rs_rARM_LR.GetRegNum())) >> lr_bit_shift));
423 } else if (IsPowerOfTwo(core_spill_mask_)) {
425 NewLIR1(kThumb2Push1, CTZ(core_spill_mask_));
427 NewLIR1(kThumb2Push, core_spill_mask_);
430 cfi_.RelOffsetForMany(DwarfCoreReg(0), 0, core_spill_mask_, kArmPointerSize);
549 bool unspill_LR_to_PC = (core_spill_mask_ & (1 << rs_rARM_LR.GetRegNum())) != 0;
551 core_spill_mask_ &= ~(1 << rs_rARM_LR.GetRegNum())
[all...] |
| target_arm.cc | 645 core_spill_mask_ |= (1 << rs_rARM_LR.GetRegNum());
[all...] |
| /art/compiler/optimizing/ |
| code_generator.h | 172 uint32_t GetCoreSpillMask() const { return core_spill_mask_; }
180 core_spill_mask_ = allocated_registers_.GetCoreRegisters() & core_callee_save_mask_;
181 DCHECK_NE(core_spill_mask_, 0u) << "At least the return address register must be saved";
343 core_spill_mask_(0),
390 return POPCOUNT(core_spill_mask_) * GetWordSize();
414 uint32_t core_spill_mask_; member in class:art::CodeGenerator
|
| code_generator_arm64.h | 234 core_spill_mask_);
|
| code_generator_arm.cc | 497 core_spill_mask_ = allocated_registers_.GetCoreRegisters() & core_callee_save_mask_;
501 core_spill_mask_ |= (1 << kCoreSavedRegisterForBaseline);
502 DCHECK_NE(core_spill_mask_, 0u) << "At least the return address register must be saved";
543 uint32_t push_mask = (core_spill_mask_ & (~(1 << PC))) | 1 << LR;
574 __ PopList(core_spill_mask_);
[all...] |
| /art/compiler/dex/quick/ |
| quick_cfi_test.cc | 93 m2l->core_spill_mask_ |= 1 << info->GetReg().GetRegNum();
|
| codegen_util.cc | [all...] |
| mir_to_lir.h | 1826 unsigned int core_spill_mask_; member in class:art::Mir2Lir
[all...] |
| ralloc_util.cc | 263 core_spill_mask_ |= (1 << reg_num);
[all...] |
| mir_to_lir.cc | 458 core_spill_mask_ = 0;
[all...] |
| /art/compiler/ |
| compiled_method.h | 348 return core_spill_mask_;
387 const uint32_t core_spill_mask_; member in class:art::FINAL
|
| compiled_method.cc | 138 frame_size_in_bytes_(frame_size_in_bytes), core_spill_mask_(core_spill_mask),
|
| /art/compiler/dex/quick/arm64/ |
| call_arm64.cc | 349 spilled_already = SpillRegs(rs_sp, core_spill_mask_, fp_spill_mask_, frame_size_);
413 UnspillRegs(rs_sp, core_spill_mask_, fp_spill_mask_, frame_size_);
428 core_spill_mask_ = (1u << rs_xLR.GetRegNum());
|
| target_arm64.cc | 670 core_spill_mask_ |= (1 << rs_xLR.GetRegNum());
|
| /art/compiler/dex/quick/x86/ |
| call_x86.cc | 290 core_spill_mask_ =
294 core_spill_mask_ = (1u << rs_rRET.GetRegNum());
|
| target_x86.cc | 466 core_spill_mask_ |= (1 << rs_rRET.GetRegNum());
740 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum());
761 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum());
[all...] |
| /art/compiler/dex/quick/mips/ |
| target_mips.cc | 517 core_spill_mask_ |= (1 << rs_rRA.GetRegNum());
848 uint32_t mask = core_spill_mask_;
868 uint32_t mask = core_spill_mask_;
[all...] |
| call_mips.cc | 389 core_spill_mask_ = (1u << TargetPtrReg(kLr).GetRegNum());
|
