| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 106 Src0 = TRI.getSubReg(Src0, SubRegIndex);
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
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| /external/llvm/lib/CodeGen/ |
| CalcSpillWeights.cpp | 49 sub = mi->getOperand(0).getSubReg();
51 hsub = mi->getOperand(1).getSubReg();
53 sub = mi->getOperand(1).getSubReg();
55 hsub = mi->getOperand(0).getSubReg();
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| TargetRegisterInfo.cpp | 194 if (RCI.getSubReg() == Idx)
233 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
242 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
252 *BestPreA = IA.getSubReg();
253 *BestPreB = IB.getSubReg();
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| PeepholeOptimizer.cpp | 369 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
646 SrcSubReg = MOSrc.getSubReg();
650 TrackSubReg = MODef.getSubReg();
695 SrcSubReg = MOInsertedReg.getSubReg();
701 if (MODef.getSubReg())
744 if (MOExtractedReg.getSubReg())
752 TrackSubReg = MODef.getSubReg();
822 if ((SrcSubReg = MOInsertedReg.getSubReg()))
[all...] |
| OptimizePHIs.cpp | 111 !SrcMI->getOperand(0).getSubReg() &&
112 !SrcMI->getOperand(1).getSubReg() &&
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| TargetInstrInfo.cpp | 140 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
141 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
142 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
353 if (FoldOp.getSubReg() || LiveOp.getSubReg())
426 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
576 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
895 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
[all...] |
| VirtRegMap.cpp | 261 unsigned SubReg = SR.getSubReg();
367 if (MO.getSubReg()) {
392 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
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| MachineInstr.cpp | 72 if (SubIdx && getSubReg())
73 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
81 if (getSubReg()) {
82 Reg = TRI.getSubReg(Reg, getSubReg());
83 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
196 getSubReg() == Other.getSubReg();
238 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
283 OS << PrintReg(getReg(), TRI, getSubReg());
[all...] |
| ExpandPostRAPseudos.cpp | 89 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
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| RegAllocFast.cpp | 677 if (!MO.getSubReg()) {
683 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
714 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
752 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
[all...] |
| RegisterCoalescer.cpp | 263 DstSub = MI->getOperand(0).getSubReg();
265 SrcSub = MI->getOperand(1).getSubReg();
268 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
271 SrcSub = MI->getOperand(2).getSubReg();
318 Dst = TRI.getSubReg(Dst, DstSub);
412 Dst = TRI.getSubReg(Dst, DstSub);
417 return TRI.getSubReg(DstReg, SrcSub) == Dst;
750 UseMI->getOperand(0).getSubReg())
848 if (Op.getSubReg() == 0 || Op.isUndef())
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIFoldOperands.cpp | 120 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
195 OpToFold.getSubReg()))
207 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) ||
224 if (UseOp.getSubReg()) {
228 if (UseOp.getSubReg() == AMDGPU::sub0) {
231 assert(UseOp.getSubReg() == AMDGPU::sub1);
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| SIFixSGPRCopies.cpp | 152 I->getOperand(0).getSubReg()));
175 Def->getOperand(1).getSubReg());
184 unsigned SrcSubReg = Copy.getOperand(1).getSubReg();
231 = inferRegClassFromDef(TRI, MRI, Reg, Op.getSubReg());
237 MI.getOperand(0).getSubReg());
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| R600ExpandSpecialInstrs.cpp | 187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
287 Src0 = TRI.getSubReg(Src0, SubRegIndex);
288 Src1 = TRI.getSubReg(Src1, SubRegIndex);
293 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
294 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
302 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
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| SIPrepareScratchRegs.cpp | 152 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
153 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
154 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
155 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
|
| /external/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const {
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 181 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
182 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
193 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
194 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 141 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
143 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
145 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
147 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(),
149 SubReg = MI->getOperand(1).getSubReg();
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 145 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg);
146 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg);
|
| HexagonInstrInfo.cpp | 448 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
450 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
454 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
456 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
597 unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
598 unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
599 unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
600 unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
602 TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
605 TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo
[all...] |
| HexagonHardwareLoops.cpp | 257 unsigned getSubReg() const {
756 SR = Start->getSubReg();
759 SR = End->getSubReg();
774 DistSR = End->getSubReg();
784 SubIB.addReg(End->getReg(), 0, End->getSubReg())
785 .addReg(Start->getReg(), 0, Start->getSubReg());
788 .addReg(Start->getReg(), 0, Start->getSubReg());
790 SubIB.addReg(End->getReg(), 0, End->getSubReg())
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXFMAMutate.cpp | 186 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg();
187 unsigned KilledProdSubReg = MI->getOperand(KilledProdOp).getSubReg();
188 unsigned OtherProdSubReg = MI->getOperand(OtherProdOp).getSubReg();
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 115 assert(MI->getOperand(0).getSubReg() == 0 &&
116 MI->getOperand(1).getSubReg() == 0 &&
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 481 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
482 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
503 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
506 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
522 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
583 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
604 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 114 MI->getOperand(0).getSubReg() == SubReg)
131 MI->getOperand(1).getSubReg() == SubReg)
329 unsigned SrcSubReg = Compare->getOperand(0).getSubReg();
|
