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    Searched refs:hasSubClassEq (Results 1 - 16 of 16) sorted by null

  /external/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 190 if (Mips::GPR32RegClass.hasSubClassEq(RC))
192 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
194 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
196 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
198 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
200 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
202 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
204 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
206 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
231 if (Mips::GPR32RegClass.hasSubClassEq(RC)
    [all...]
Mips16InstrInfo.cpp 103 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
122 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 617 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
618 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
619 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
620 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
651 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
652 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
654 PPC::GPRCRegClass.hasSubClassEq(RC) ||
655 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
851 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
852 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC))
    [all...]
PPCVSXCopy.cpp 60 return RC->hasSubClassEq(MRI.getRegClass(Reg));
  /external/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 313 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
387 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||
388 AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
401 if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||
402 AArch64::FPR32RegClass.hasSubClassEq(RC)) {
735 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
    [all...]
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 128 return RC != this && hasSubClassEq(RC);
131 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
133 bool hasSubClassEq(const TargetRegisterClass *RC) const {
147 return RC->hasSubClassEq(this);
151 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
    [all...]
  /external/llvm/lib/Target/Sparc/
SparcInstrInfo.cpp 375 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
378 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
412 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
415 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
SparcISelLowering.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 899 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
903 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
911 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
915 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
    [all...]
Thumb2InstrInfo.cpp 149 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
190 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
ThumbRegisterInfo.cpp 49 if (ARM::tGPRRegClass.hasSubClassEq(RC))
  /external/llvm/lib/Target/X86/
X86InstrInfo.cpp     [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 501 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
505 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
509 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
    [all...]
  /external/llvm/lib/CodeGen/
MachineFunction.cpp 448 RC->hasSubClassEq(VRegRC))) &&
    [all...]
TargetInstrInfo.cpp 368 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 550 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
    [all...]

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