| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 191 return isReg() ? 0 : SubReg_TargetFlags;
194 assert(!isReg() && "Register operands can't have target flags");
199 assert(!isReg() && "Register operands can't have target flags");
226 /// isReg - Tests if this is a MO_Register operand.
227 bool isReg() const { return OpKind == MO_Register; }
265 assert(isReg() && "This is not a register operand!");
270 assert(isReg() && "Wrong MachineOperand accessor");
275 assert(isReg() && "Wrong MachineOperand accessor");
280 assert(isReg() && "Wrong MachineOperand accessor");
285 assert(isReg() && "Wrong MachineOperand accessor")
[all...] |
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) {
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
191 if (Op.isReg()) {
296 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
298 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
301 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
304 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
307 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
310 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS)
[all...] |
| /external/llvm/lib/CodeGen/ |
| LivePhysRegs.cpp | 40 if (O->isReg()) {
53 if (!O->isReg() || !O->readsReg() || O->isUndef())
70 if (O->isReg()) {
|
| AntiDepBreaker.h | 60 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
|
| MachineInstr.cpp | 92 assert(isReg() && "Wrong MachineOperand accessor");
112 if (!isReg() || !isOnRegUseList())
127 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
136 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
157 bool WasReg = isReg();
640 if (MO.isReg())
649 if (MO.isReg())
696 bool isImpReg = Op.isReg() && Op.isImplicit();
698 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
743 if (NewMO->isReg()) {
[all...] |
| DeadMachineInstructionElim.cpp | 74 if (MO.isReg() && MO.isDef()) {
144 if (MO.isReg() && MO.isDef()) {
163 if (MO.isReg() && MO.isUse()) {
|
| /external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 18 if (Op.isReg()) {
|
| /external/llvm/lib/Target/R600/ |
| SIFoldOperands.cpp | 66 assert(FoldOp->isReg());
110 assert(Old.isReg());
182 if (!FoldingImm && !OpToFold.isReg())
193 if (OpToFold.isReg() &&
207 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) ||
278 assert(Fold.OpToFold && Fold.OpToFold->isReg());
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 174 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
186 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
199 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
212 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
224 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
237 assert(MI.getOperand(OpNo+1).isReg());
256 assert(MI.getOperand(OpNo+1).isReg());
276 assert(MI.getOperand(OpNo+1).isReg());
292 assert(MI.getOperand(OpNo+1).isReg());
308 assert(MI.getOperand(OpNo+1).isReg());
[all...] |
| /sdk/find_java2/FindJava2/ |
| FindJava2.cpp | 120 bool isReg = (p == javaPath);
121 if (isReg) {
124 _tprintf(_T("%c [%s] %s\n"), isReg ? '*' : ' ', p.getVersion(), p.mPath);
|
| /external/llvm/include/llvm/MC/MCParser/ |
| MCParsedAsmOperand.h | 47 /// isReg - Is this a register operand?
48 virtual bool isReg() const = 0;
|
| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| SparcInstPrinter.cpp | 62 if (!MI->getOperand(0).isReg())
86 || (!MI->getOperand(0).isReg())
112 if (MO.isReg()) {
139 if (MO.isReg() && MO.getReg() == SP::G0)
|
| /external/llvm/lib/Target/BPF/InstPrinter/ |
| BPFInstPrinter.cpp | 54 if (Op.isReg()) {
75 assert(RegOp.isReg() && "Register operand not a register");
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 250 bool isReg() const { return Kind == CV_Register; }
254 assert(isReg() && "Wrong CountValue accessor");
258 assert(isReg() && "Wrong CountValue accessor");
267 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
522 if (Op1.isReg()) {
559 if (InitialValue->isReg()) {
586 if (InitialValue->isReg()) {
593 if (EndValue->isReg()) {
619 if (Start->isReg()) {
624 if (End->isReg()) {
[all...] |
| HexagonAsmPrinter.cpp | 131 if (!MI->getOperand(OpNo).isReg() ||
133 !MI->getOperand(OpNo+1).isReg())
160 if (Base.isReg())
|
| HexagonNewValueJump.cpp | 150 if (II->getOperand(i).isReg() &&
466 MI->getOperand(0).isReg() &&
474 isSecondOpReg = MI->getOperand(2).isReg();
508 if (MI->getOperand(0).isReg() &&
565 if (MO.isReg() && MO.isUse()) {
572 if (localMO.isReg() && localMO.isUse() &&
627 if (cmpInstr->getOperand(0).isReg() &&
630 if (cmpInstr->getOperand(1).isReg() &&
|
| HexagonExpandCondsets.cpp | 268 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
300 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
328 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
357 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
428 if (Op.isReg() && Op.isDef())
505 if (!Op.isReg() || !Op.isUse() || Op.isImplicit() || Op.isUndef())
544 if (!Op.isReg() || !Op.isDef())
622 if (!Op.isReg() || !Op.isUse())
643 if (SO.isReg()) {
749 if (!Op.isReg() || !Op.isDef()
[all...] |
| HexagonVLIWPacketizer.cpp | 354 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
480 if (MI->getOperand(opNum).isReg() &&
486 if (MI->getOperand(opNum).isReg() &&
495 assert(MI->getOperand(1).isReg() &&
501 assert(MI->getOperand(0).isReg() &&
544 if (GetStoreValueOperand(MI).isReg() &&
608 if ( PacketMI->getOperand(opNum).isReg())
620 if ( MI->getOperand(opNum).isReg())
674 if (MI->getOperand(opNum).isReg() &&
688 GetStoreValueOperand(MI).isReg() &
[all...] |
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCCodeEmitter.cpp | 117 if (MO.isReg())
144 if (MO.isReg() || MO.isImm())
179 if (MO.isReg() || MO.isImm())
192 if (MO.isReg() || MO.isImm())
204 if (MO.isReg() || MO.isImm())
|
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 56 bool isReg() const { return Kind == kRegister; }
64 assert(isReg() && "This is not a register operand!");
70 assert(isReg() && "This is not a register operand!");
|
| MachineLocation.h | 53 bool isReg() const { return IsRegister; }
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 55 if (MO.isReg() && MO.isDef())
81 if (MO.isReg() && MO.isDead() && MO.isDef()) {
|
| /external/llvm/lib/MC/ |
| MCInst.cpp | 22 else if (isReg())
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsELFStreamer.cpp | 28 if (!Op.isReg())
|
| /external/llvm/lib/Target/XCore/InstPrinter/ |
| XCoreInstPrinter.cpp | 75 if (Op.isReg()) {
|
