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    Searched refs:next_insn (Results 1 - 6 of 6) sorted by null

  /art/compiler/linker/arm64/
relative_patcher_arm64.cc 265 uint32_t next_insn = GetInsn(code, literal_offset + 4u); local
272 if ((next_insn & 0xffc00000) == 0xb9400000 &&
273 (((next_insn >> 5) ^ adrp) & 0x1f) == 0) {
278 if ((next_insn & 0xff000000) == 0x18000000) {
283 if ((next_insn & 0xff000000) == 0x58000000) {
284 bool is_aligned_load = (((next_offset >> 2) ^ (next_insn >> 5)) & 1) == 0;
290 if ((next_insn & 0xbfc003e0) == 0xb94003e0) {
  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_eu_emit.c 698 #define next_insn brw_next_insn macro
734 struct brw_instruction *insn = next_insn(p, opcode);
746 struct brw_instruction *insn = next_insn(p, opcode);
771 struct brw_instruction *insn = next_insn(p, opcode);
869 rnd = next_insn(p, BRW_OPCODE_##OP); \
993 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP);
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  /external/libunwind/src/ia64/
Gscript.c 519 struct ia64_script_insn *ip, *limit, next_insn; local
529 next_insn = *ip;
534 opc = next_insn.opc;
535 dst = next_insn.dst;
536 val = next_insn.val;
537 next_insn = *ip;
  /art/runtime/verifier/
method_verifier.h 651 * Control can transfer to "next_insn". Merge the registers from merge_line into the table at
652 * next_insn, and set the changed flag on the target address if any of the registers were changed.
657 bool UpdateRegisters(uint32_t next_insn, RegisterLine* merge_line, bool update_merge_line)
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method_verifier.cc     [all...]
  /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/
rtl.h 363 /* FIXME: the "NEXT_INSN (PREV_INSN (X)) == X" condition shouldn't be needed.
370 && NEXT_INSN (PREV_INSN (X)) == X \
828 #define NEXT_INSN(INSN) XEXP (INSN, 2)
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