| /art/compiler/dex/quick/arm/ |
| utility_arm.cc | 422 LIR* ArmMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) {
423 UNUSED(r_dest, r_base, offset, move_type);
428 LIR* ArmMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {
429 UNUSED(r_base, offset, r_src, move_type);
748 LIR* ArmMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest,
750 bool all_low_regs = r_base.Low8() && r_index.Low8() && r_dest.Low8();
778 NewLIR4(kThumb2AddRRR, reg_ptr.GetReg(), r_base.GetReg(), r_index.GetReg(),
781 OpRegRegReg(kOpAdd, reg_ptr, r_base, r_index);
807 load = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg());
809 load = NewLIR4(opcode, r_dest.GetReg(), r_base.GetReg(), r_index.GetReg(), scale)
[all...] |
| codegen_arm.h | 71 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
73 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
77 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
79 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
206 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
213 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
214 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
219 LIR* OpVldm(RegStorage r_base, int count);
220 LIR* OpVstm(RegStorage r_base, int count);
223 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size)
[all...] |
| call_arm.cc | 45 * adr r_base, <table>
49 * ldmia r_base!, {r_key, r_disp}
69 RegStorage r_base = AllocTemp(); local
80 NewLIR3(kThumb2Adr, r_base.GetReg(), 0, WrapPointer(tab_rec));
87 NewLIR2(kThumb2LdmiaWB, r_base.GetReg(), (1 << r_key.GetRegNum()) | (1 << r_disp.GetRegNum()));
|
| int_arm.cc | [all...] |
| /art/compiler/dex/quick/mips/ |
| utility_mips.cc | 523 LIR* MipsMir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset,
525 UNUSED(r_dest, r_base, offset, move_type);
530 LIR* MipsMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {
531 UNUSED(r_base, offset, r_src, move_type);
569 LIR* MipsMir2Lir::LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest,
589 first = NewLIR3(kMips64Daddu, t_reg.GetReg() , r_base.GetReg(), r_index.GetReg());
591 first = NewLIR3(kMipsAddu, t_reg.GetReg() , r_base.GetReg(), r_index.GetReg());
595 NewLIR3(kMips64Daddu, t_reg.GetReg() , r_base.GetReg(), t_reg.GetReg());
599 first = NewLIR3(kMipsAddu, t_reg.GetReg() , r_base.GetReg(), r_index.GetReg());
602 NewLIR3(kMipsAddu, t_reg.GetReg() , r_base.GetReg(), t_reg.GetReg())
[all...] |
| codegen_mips.h | 83 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size,
85 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
90 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
92 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
94 LIR* GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest);
95 LIR* GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src);
203 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
210 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type);
211 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type);
216 LIR* OpVldm(RegStorage r_base, int count)
[all...] |
| call_mips.cc | 58 * addiu r_base, rRA, <table> - <BaseLabel> ; table relative to BaseLabel
59 addu r_end, r_end, r_base ; end of table
62 * beq r_base, r_end, done
63 * lw r_key, 0(r_base)
64 * addu r_base, 8
66 * lw r_disp, -4(r_base)
108 RegStorage r_base = AllocPtrSizeTemp(); local
109 NewLIR4(kMipsDelta, r_base.GetReg(), 0, WrapPointer(base_label), WrapPointer(tab_rec));
110 OpRegRegReg(kOpAdd, r_end, r_end, r_base);
118 LIR* exit_branch = OpCmpBranch(kCondEq, r_base, r_end, nullptr)
197 RegStorage r_base = AllocPtrSizeTemp(); local
[all...] |
| int_mips.cc | 417 LIR* MipsMir2Lir::OpVldm(RegStorage r_base, int count) {
418 UNUSED(r_base, count);
423 LIR* MipsMir2Lir::OpVstm(RegStorage r_base, int count) {
424 UNUSED(r_base, count);
|
| target_mips.cc | 789 LIR* MipsMir2Lir::GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest) {
797 OpRegRegImm(kOpAdd, reg_ptr, r_base, displacement);
811 LIR* MipsMir2Lir::GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src) {
821 OpRegRegImm(kOpAdd, temp_ptr, r_base, displacement);
[all...] |
| /art/compiler/dex/quick/x86/ |
| utility_x86.cc | 257 LIR* X86Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) {
258 DCHECK(!r_base.IsFloat());
306 return NewLIR3(opcode, dest, r_base.GetReg(), offset);
309 LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) {
310 DCHECK(!r_base.IsFloat());
359 return NewLIR3(opcode, r_base.GetReg(), offset, src);
370 LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) {
390 LIR *l = NewLIR3(opcode, r_dest.GetReg(), r_base.GetReg(), offset);
392 DCHECK_EQ(r_base, cu_->target64 ? rs_rX86_SP_64 : rs_rX86_SP_32);
556 LIR* X86Mir2Lir::OpMem(OpKind op, RegStorage r_base, int disp)
[all...] |
| codegen_x86.h | 92 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
94 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
99 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
101 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
302 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
309 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE;
310 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE;
315 LIR* OpVldm(RegStorage r_base, int count) OVERRIDE;
316 LIR* OpVstm(RegStorage r_base, int count) OVERRIDE;
429 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement
[all...] |
| int_x86.cc | 1976 int r_base = rs_rX86_SP_32.GetReg(); local
2019 int r_base = rs_rX86_SP_32.GetReg(); local
2869 int r_base = rs_rX86_SP_32.GetReg(); local
2900 int r_base = rs_rX86_SP_32.GetReg(); local
[all...] |
| target_x86.cc | 905 int r_base = rs_rX86_SP_32.GetReg(); local
909 LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo);
912 store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi);
[all...] |
| /art/compiler/dex/quick/arm64/ |
| utility_arm64.cc | 675 LIR* Arm64Mir2Lir::OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset,
677 UNUSED(r_dest, r_base, offset, move_type);
682 LIR* Arm64Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src,
684 UNUSED(r_base, offset, r_src, move_type);
[all...] |
| codegen_arm64.h | 67 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
69 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale,
73 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
75 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale,
209 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
216 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE;
217 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE;
222 LIR* OpVldm(RegStorage r_base, int count) OVERRIDE;
223 LIR* OpVstm(RegStorage r_base, int count) OVERRIDE;
384 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size)
[all...] |
| call_arm64.cc | 41 * adr r_base, <table>
46 * ldp r_key, r_disp, [r_base], #8
50 * adr r_base, #0 ; This is the instruction from which we compute displacements
51 * add r_base, r_disp
52 * br r_base
68 RegStorage r_base = AllocTempWide(); local
73 NewLIR3(kA64Adr2xd, r_base.GetReg(), 0, WrapPointer(tab_rec));
83 NewLIR4(kA64LdpPost4rrXD, r_key.GetReg(), r_disp.GetReg(), r_base.GetReg(), 2);
91 LIR* switch_label = NewLIR3(kA64Adr2xd, r_base.GetReg(), 0, -1);
95 OpRegRegRegExtend(kOpAdd, r_base, r_base, As64BitReg(r_disp), kA64Sxtw, 0U)
[all...] |
| int_arm64.cc | [all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.h | [all...] |
| gen_common.cc | 96 RegStorage r_base = TargetReg(kArg0, kRef); local
97 LockTemp(r_base);
100 OpPcRelDexCacheArrayLoad(cu_->dex_file, offset, r_base, false);
103 RegStorage r_method = LoadCurrMethodWithHint(r_base);
104 LoadRefDisp(r_method, ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), r_base,
107 LoadRefDisp(r_base, offset_of_field, r_base, kNotVolatile);
109 // r_base now points at static storage (Class*) or null if the type is not yet resolved.
112 // Check if r_base is null.
113 unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, nullptr)
691 RegStorage r_base; local
769 RegStorage r_base; local
[all...] |
| /external/valgrind/VEX/priv/ |
| host_ppc_defs.c | 4785 UInt opc2, v_reg, r_idx, r_base; local
5222 UInt r_idx, r_base; local
[all...] |
| host_mips_isel.c | 734 HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1); local
736 return MIPSAMode_RR(r_idx, r_base);
753 HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1); local
756 return MIPSAMode_RR(r_idx, r_base);
[all...] |
| host_ppc_isel.c | 2564 HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); local
2588 HReg r_base = iselWordExpr_R(env, e->Iex.Binop.arg1, IEndianess); local
[all...] |
