| /external/v8/test/cctest/ |
| test-utils-arm64.cc | 267 void Clobber(MacroAssembler* masm, RegList reg_list, uint64_t const value) {
270 if (reg_list & (1UL << i)) {
290 void ClobberFP(MacroAssembler* masm, RegList reg_list, double const value) {
293 if (reg_list & (1UL << i)) {
309 void Clobber(MacroAssembler* masm, CPURegList reg_list) {
310 if (reg_list.type() == CPURegister::kRegister) {
312 Clobber(masm, reg_list.list());
313 } else if (reg_list.type() == CPURegister::kFPRegister) {
315 ClobberFP(masm, reg_list.list());
|
| test-utils-arm64.h | 221 void Clobber(MacroAssembler* masm, RegList reg_list,
225 void ClobberFP(MacroAssembler* masm, RegList reg_list,
231 void Clobber(MacroAssembler* masm, CPURegList reg_list);
|
| /external/vixl/test/ |
| test-utils-a64.cc | 299 void Clobber(MacroAssembler* masm, RegList reg_list, uint64_t const value) {
302 if (reg_list & (UINT64_C(1) << i)) {
322 void ClobberFP(MacroAssembler* masm, RegList reg_list, double const value) {
325 if (reg_list & (UINT64_C(1) << i)) {
341 void Clobber(MacroAssembler* masm, CPURegList reg_list) {
342 if (reg_list.type() == CPURegister::kRegister) {
344 Clobber(masm, reg_list.list());
345 } else if (reg_list.type() == CPURegister::kVRegister) {
347 ClobberFP(masm, reg_list.list());
|
| test-utils-a64.h | 243 void Clobber(MacroAssembler* masm, RegList reg_list,
247 void ClobberFP(MacroAssembler* masm, RegList reg_list,
253 void Clobber(MacroAssembler* masm, CPURegList reg_list);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600GenRegisterInfo.pl | 174 my @reg_list;
181 $reg_list[$i] = $name;
183 return @reg_list;
|
| SIGenRegisterInfo.pl | 283 my $reg_list = join(', ', @registers);
285 print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n (add $reg_list)\n>{\n";
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerProxy.cpp | 236 void ARMAssemblerProxy::LDM(int cc, int dir, int Rn, int W, uint32_t reg_list) {
237 mTarget->LDM(cc, dir, Rn, W, reg_list);
239 void ARMAssemblerProxy::STM(int cc, int dir, int Rn, int W, uint32_t reg_list) {
240 mTarget->STM(cc, dir, Rn, W, reg_list);
|
| ARMAssembler.h | 134 int Rn, int W, uint32_t reg_list);
136 int Rn, int W, uint32_t reg_list);
|
| ARMAssemblerProxy.h | 121 int Rn, int W, uint32_t reg_list);
123 int Rn, int W, uint32_t reg_list);
|
| ARMAssembler.cpp | 332 int Rn, int W, uint32_t reg_list)
337 (uint32_t(U[dir])<<23) | (1<<20) | (W<<21) | (Rn<<16) | reg_list;
341 int Rn, int W, uint32_t reg_list)
346 (uint32_t(U[dir])<<23) | (0<<20) | (W<<21) | (Rn<<16) | reg_list;
|
| ARMAssemblerInterface.h | 173 int Rn, int W, uint32_t reg_list) = 0;
175 int Rn, int W, uint32_t reg_list) = 0;
|
| Arm64Assembler.h | 151 int Rn, int W, uint32_t reg_list);
153 int Rn, int W, uint32_t reg_list);
|
| Arm64Assembler.cpp | 682 int Rn, int W, uint32_t reg_list)
693 if((reg_list & (1 << i)))
703 int Rn, int W, uint32_t reg_list)
714 if((reg_list & (1 << i)))
[all...] |
| MIPSAssembler.h | 133 int Rn, int W, uint32_t reg_list);
135 int Rn, int W, uint32_t reg_list);
|
| MIPSAssembler.cpp | 974 int Rn, int W, uint32_t reg_list)
979 // (uint32_t(U[dir])<<23) | (1<<20) | (W<<21) | (Rn<<16) | reg_list;
986 int Rn, int W, uint32_t reg_list)
991 // (uint32_t(U[dir])<<23) | (0<<20) | (W<<21) | (Rn<<16) | reg_list;
[all...] |
| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| arm64_assembler_test.cpp | 752 uint32_t reg_list[] = {0,1,12,14}; local
[all...] |
| /art/compiler/dex/quick/arm/ |
| target_arm.cc | 150 constexpr ResourceMask ArmMir2Lir::EncodeArmRegList(int reg_list) {
151 return ResourceMask::RawMask(static_cast<uint64_t >(reg_list), 0u);
154 constexpr ResourceMask ArmMir2Lir::EncodeArmRegFpcsList(int reg_list) {
155 return ResourceMask::RawMask(static_cast<uint64_t >(reg_list) << kArmFPReg16, 0u);
[all...] |
| codegen_arm.h | 305 static constexpr ResourceMask EncodeArmRegList(int reg_list);
306 static constexpr ResourceMask EncodeArmRegFpcsList(int reg_list);
|
