| /art/compiler/dex/quick/ |
| ralloc_util.cc | 156 DumpRegPool(®_pool_->core_regs_);
157 DumpRegPool(®_pool_->core64_regs_);
161 DumpRegPool(®_pool_->sp_regs_);
162 DumpRegPool(®_pool_->dp_regs_);
280 for (RegisterInfo* info : reg_pool_->core_regs_) {
312 for (RegisterInfo* info : reg_pool_->sp_regs_) {
398 return AllocTempBody(reg_pool_->core_regs_, ®_pool_->next_core_reg_, required);
403 if (reg_pool_->core64_regs_.size() != 0) {
404 res = AllocTempBody(reg_pool_->core64_regs_, ®_pool_->next_core64_reg_, required)
[all...] |
| quick_cfi_test.cc | 91 for (const auto& info : m2l->reg_pool_->core_regs_) {
97 for (const auto& info : m2l->reg_pool_->sp_regs_) {
|
| codegen_util.cc | [all...] |
| mir_to_lir.cc | [all...] |
| mir_to_lir.h | 1807 std::unique_ptr<RegisterPool> reg_pool_; member in class:art::Mir2Lir
[all...] |
| /art/compiler/dex/quick/arm/ |
| target_arm.cc | 597 reg_pool_.reset(new (arena_) RegisterPool(this, arena_, core_regs, empty_pool /* core64 */,
606 for (RegisterInfo* info : reg_pool_->sp_regs_) {
633 reg_pool_->next_core_reg_ = 2;
634 reg_pool_->next_sp_reg_ = 0;
635 reg_pool_->next_dp_reg_ = 0;
866 for (RegisterInfo* info : reg_pool_->dp_regs_) {
890 for (RegisterInfo* info : reg_pool_->sp_regs_) {
[all...] |
| /art/compiler/dex/quick/mips/ |
| target_mips.cc | 686 reg_pool_.reset(new (arena_) RegisterPool(this, arena_, core_regs_64, core_regs_64d, sp_regs_64,
692 for (RegisterInfo* info : reg_pool_->sp_regs_) {
706 for (RegisterInfo* info : reg_pool_->core_regs_) {
718 reg_pool_.reset(new (arena_) RegisterPool(this, arena_, core_regs_32, empty_pool, // core64
727 for (RegisterInfo* info : reg_pool_->sp_regs_) {
749 reg_pool_->next_core_reg_ = 2;
750 reg_pool_->next_sp_reg_ = 2;
752 reg_pool_->next_dp_reg_ = 1;
754 reg_pool_->next_dp_reg_ = 2;
[all...] |
| /art/compiler/dex/quick/arm64/ |
| target_arm64.cc | 625 reg_pool_.reset(new (arena_) RegisterPool(this, arena_, core_regs, core64_regs, sp_regs, dp_regs,
631 for (RegisterInfo* info : reg_pool_->sp_regs_) {
644 for (RegisterInfo* info : reg_pool_->core_regs_) {
658 reg_pool_->next_core_reg_ = 2;
659 reg_pool_->next_sp_reg_ = 0;
660 reg_pool_->next_dp_reg_ = 0;
|
| /art/compiler/dex/quick/x86/ |
| target_x86.cc | 643 reg_pool_.reset(new (arena_) RegisterPool(this, arena_, core_regs_64, core_regs_64q, sp_regs_64,
648 reg_pool_.reset(new (arena_) RegisterPool(this, arena_, core_regs_32, empty_pool, sp_regs_32,
676 for (RegisterInfo* info : reg_pool_->sp_regs_) {
696 for (RegisterInfo* info : reg_pool_->core_regs_) {
711 reg_pool_->next_core_reg_ = 2;
712 reg_pool_->next_sp_reg_ = 2;
713 reg_pool_->next_dp_reg_ = 1;
[all...] |
