| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_fs_reg_allocate.cpp | 34 assign_reg(int *reg_hw_locations, fs_reg *reg, int reg_width)
38 reg->reg = reg_hw_locations[reg->reg] + reg->reg_offset * reg_width;
48 int reg_width = c->dispatch_width / 8; local
51 hw_reg_mapping[0] = ALIGN(this->first_non_payload_grf, reg_width);
54 this->virtual_grf_sizes[i - 1] * reg_width);
61 assign_reg(hw_reg_mapping, &inst->dst, reg_width);
62 assign_reg(hw_reg_mapping, &inst->src[0], reg_width);
63 assign_reg(hw_reg_mapping, &inst->src[1], reg_width);
64 assign_reg(hw_reg_mapping, &inst->src[2], reg_width);
78 int reg_width,
157 int reg_width = c->dispatch_width \/ 8; local
[all...] |
| brw_fs_visitor.cpp | 924 int reg_width = c->dispatch_width / 8; local
938 fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
955 fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
960 mlen += vector_elements * reg_width;
963 mlen = MAX2(mlen, header_present + 4 * reg_width);
966 mlen += reg_width;
975 mlen = MAX2(mlen, header_present + 4 * reg_width);
977 mlen += reg_width;
982 mlen = MAX2(mlen, header_present + 4 * reg_width);
984 mlen += reg_width;
1044 int reg_width = c->dispatch_width \/ 8; local
1836 int reg_width = c->dispatch_width \/ 8; local
1959 int reg_width = c->dispatch_width \/ 8; local
2043 int reg_width = c->dispatch_width \/ 8; local
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIGenRegisterInfo.pl | 248 my ($reg_width, $sub_reg_ref, @types) = @_;
249 return print_reg_class('SReg', 'SGPR', $reg_width, $SGPR_COUNT, $sub_reg_ref, @types);
253 my ($reg_width, $sub_reg_ref, @types) = @_;
254 return print_reg_class('VReg', 'VGPR', $reg_width, $VGPR_COUNT, $sub_reg_ref, @types);
258 my ($class_prefix, $reg_prefix, $reg_width, $reg_count, $sub_reg_ref, @types) = @_;
260 my $component_count = $reg_width / 32;
263 my $reg_name = $reg_prefix . $i . '_' . $reg_width;
269 print "def $reg_name : $reg_prefix\_$reg_width <$i, \"$reg_name\", [ ", join(',', @sub_regs) , "]>;\n";
274 if ($class_prefix eq 'SReg' and $reg_width == 64) {
279 if ($class_prefix eq 'SReg' and $reg_width == 64)
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_blit.c | 260 float reg_width, float reg_height,
264 buf[1] = buf[0] + reg_width / img_width;
278 unsigned reg_width, unsigned reg_height,
287 reg_width, reg_height,
295 verts[4] = dst_x_offset + reg_width;
300 verts[8] = dst_x_offset + reg_width;
358 unsigned reg_width,
375 if (reg_width + src_x_offset > src_width)
376 reg_width = src_width - src_x_offset;
379 if (reg_width + dst_x_offset > dst_width
[all...] |
| radeon_common_context.h | 495 unsigned reg_width,
|
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_blit.c | 385 float reg_width, float reg_height,
389 buf[1] = buf[0] + reg_width / img_width;
403 unsigned reg_width, unsigned reg_height,
412 reg_width, reg_height,
420 verts[4] = dst_x_offset + reg_width;
425 verts[8] = dst_x_offset + reg_width;
480 unsigned reg_width,
497 if (reg_width + src_x_offset > src_width)
498 reg_width = src_width - src_x_offset;
501 if (reg_width + dst_x_offset > dst_width
[all...] |
| /art/compiler/dex/quick/ |
| codegen_util.cc | 817 uint32_t reg_width = static_cast<uint32_t>((max_ref_vreg + 8) / 8); local
820 max_native_offset, reg_width);
833 references_buffer.resize(reg_width);
840 for (size_t i = 0; i != reg_width; ++i) {
[all...] |
| /external/vixl/src/vixl/a64/ |
| simulator-a64.h | [all...] |
