| /art/compiler/utils/x86_64/ |
| assembler_x86_64.h | 567 void sarq(CpuRegister reg, const Immediate& imm);
568 void sarq(CpuRegister operand, CpuRegister shifter);
|
| assembler_x86_64_test.cc | 475 // Sarq only allows CL as the shift count.
483 assembler->sarq(*reg, shifter);
484 str << "sarq %cl, %" << assembler_test->GetRegisterName(*reg) << "\n";
491 DriverFn(&sarq_fn, "sarq");
495 DriverStr(RepeatRI(&x86_64::X86_64Assembler::sarq, 1U, "sarq ${imm}, %{reg}"), "sarqi");
[all...] |
| assembler_x86_64.cc | 1839 void X86_64Assembler::sarq(CpuRegister reg, const Immediate& imm) { function in class:art::x86_64::X86_64Assembler
1844 void X86_64Assembler::sarq(CpuRegister operand, CpuRegister shifter) { function in class:art::x86_64::X86_64Assembler
[all...] |
| /external/v8/test/cctest/ |
| test-disasm-x64.cc | 188 __ sarq(rdx, Immediate(1));
189 __ sarq(rdx, Immediate(6));
|
| /external/boringssl/linux-x86_64/crypto/bn/ |
| x86_64-mont5.S | 729 sarq $3+2,%rcx
1605 sarq $3+2,%rcx
|
| /external/boringssl/mac-x86_64/crypto/bn/ |
| x86_64-mont5.S | 728 sarq $3+2,%rcx
1604 sarq $3+2,%rcx
|
| /external/v8/src/compiler/x64/ |
| code-generator-x64.cc | 390 ASSEMBLE_SHIFT(sarq, 6);
|
| /art/compiler/optimizing/ |
| code_generator_x86_64.cc | [all...] |
| intrinsics_x86_64.cc | 358 __ sarq(mask, Immediate(63));
[all...] |
| /external/v8/src/x64/ |
| macro-assembler-x64.cc | [all...] |
