| /external/clang/test/CodeGen/ |
| systemz-abi-vector.c | 19 typedef __attribute__((vector_size(8))) float v2f32; typedef
84 v2f32 pass_v2f32(v2f32 arg) { return arg; }
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 192 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
195 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
199 // Complex: to v2f32
200 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
201 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
202 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
203 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
204 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
205 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
223 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }
[all...] |
| AArch64ISelDAGToDAG.cpp | [all...] |
| AArch64ISelLowering.cpp | 104 addDRTypeForNEON(MVT::v2f32);
606 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
622 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
637 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 97 v2f32 = 46, // 2 x f32 enumerator in enum:llvm::MVT::SimpleValueType
219 SimpleTy == MVT::v4f16 || SimpleTy == MVT::v2f32 ||
317 case v2f32:
365 case v2f32:
420 case v2f32:
572 if (NumElements == 2) return MVT::v2f32;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 58 { ISD::FP_EXTEND, MVT::v2f32, 2 },
108 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
109 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
110 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
111 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
112 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
113 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
347 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
369 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1},
|
| ARMISelLowering.cpp | 430 addDRTypeForNEON(MVT::v2f32);
498 // Mark v2f32 intrinsics.
499 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
500 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
501 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
502 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
503 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
504 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
505 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
506 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand)
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 161 case MVT::v2f32: return "v2f32";
232 case MVT::v2f32: return VectorType::get(Type::getFloatTy(Context), 2);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 63 (int)MVT::v2f32,
91 (int)MVT::v2f32,
502 FLTTY = MVT::v2f32;
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 106 case MVT::v2f32: return "MVT::v2f32";
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 150 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
190 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
356 MVT::v2f32, MVT::v4f32
[all...] |
| R600ISelLowering.cpp | 40 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
151 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom);
156 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom);
699 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32,
[all...] |
| SIISelLowering.cpp | 52 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 70 case MVT::v2f32:
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
