| /external/llvm/test/MC/Mips/msa/ |
| set-msa-directive.s | 4 # CHECK: addvi.b $w14, $w12, 14
8 # CHECK: subvi.b $w14, $w12, 14
14 addvi.b $w14, $w12, 14
19 subvi.b $w14, $w12, 14
|
| test_2rf.s | 3 # CHECK: fclass.w $w26, $w12 # encoding: [0x7b,0x20,0x66,0x9e]
10 # CHECK: ffint_s.d $w12, $w15 # encoding: [0x7b,0x3d,0x7b,0x1e]
14 # CHECK: ffql.d $w12, $w13 # encoding: [0x7b,0x35,0x6b,0x1e]
23 # CHECK: frsqrt.w $w12, $w17 # encoding: [0x7b,0x28,0x8b,0x1e]
26 # CHECK: fsqrt.d $w15, $w12 # encoding: [0x7b,0x27,0x63,0xde]
32 # CHECK: ftrunc_s.d $w12, $w27 # encoding: [0x7b,0x23,0xdb,0x1e]
36 fclass.w $w26, $w12
43 ffint_s.d $w12, $w15
47 ffql.d $w12, $w13
56 frsqrt.w $w12, $w1
[all...] |
| test_i5.s | 9 # CHECK: ceqi.w $w12, $w1, -1 # encoding: [0x78,0x5f,0x0b,0x07]
11 # CHECK: clei_s.b $w12, $w16, 1 # encoding: [0x7a,0x01,0x83,0x07]
21 # CHECK: clti_s.w $w12, $w12, 11 # encoding: [0x79,0x4b,0x63,0x07]
41 # CHECK: mini_u.w $w11, $w12, 26 # encoding: [0x7a,0xda,0x62,0xc6]
45 # CHECK: subvi.w $w12, $w10, 11 # encoding: [0x78,0xcb,0x53,0x06]
54 ceqi.w $w12, $w1, -1
56 clei_s.b $w12, $w16, 1
66 clti_s.w $w12, $w12, 1
[all...] |
| set-msa-directive-bad.s | 5 addvi.b $w14, $w12, 14 # CHECK: error: instruction requires a CPU feature not currently enabled
|
| test_3r.s | 26 # CHECK: asub_s.d $w13, $w12, $w12 # encoding: [0x7a,0x6c,0x63,0x51]
37 # CHECK: ave_u.w $w11, $w12, $w11 # encoding: [0x7a,0xcb,0x62,0xd0]
54 # CHECK: binsl.d $w23, $w20, $w12 # encoding: [0x7b,0x6c,0xa5,0xcd]
64 # CHECK: bset.h $w14, $w12, $w6 # encoding: [0x7a,0x26,0x63,0x8d]
65 # CHECK: bset.w $w31, $w9, $w12 # encoding: [0x7a,0x4c,0x4f,0xcd]
82 # CHECK: clt_s.d $w7, $w30, $w12 # encoding: [0x79,0x6c,0xf1,0xcf]
102 # CHECK: dpadd_s.w $w10, $w1, $w12 # encoding: [0x79,0x4c,0x0a,0x93]
107 # CHECK: dpsub_s.h $w4, $w11, $w12 # encoding: [0x7a,0x2c,0x59,0x13]
109 # CHECK: dpsub_s.d $w31, $w12, $w28 # encoding: [0x7a,0x7c,0x67,0xd3
[all...] |
| test_elm.s | 12 # CHECK: sldi.d $w4, $w12[0] # encoding: [0x78,0x38,0x61,0x19]
28 sldi.d $w4, $w12[0]
|
| test_3rf.s | 53 # CHECK: fslt.w $w12, $w5, $w6 # encoding: [0x7b,0x06,0x2b,0x1a]
55 # CHECK: fsne.w $w30, $w1, $w12 # encoding: [0x7a,0xcc,0x0f,0x9c]
58 # CHECK: fsor.d $w12, $w24, $w11 # encoding: [0x7a,0x6b,0xc3,0x1c]
76 # CHECK: maddr_q.w $w29, $w12, $w16 # encoding: [0x7b,0x70,0x67,0x5c]
79 # CHECK: msubr_q.h $w12, $w21, $w11 # encoding: [0x7b,0x8b,0xab,0x1c]
136 fslt.w $w12, $w5, $w6
138 fsne.w $w30, $w1, $w12
141 fsor.d $w12, $w24, $w11
159 maddr_q.w $w29, $w12, $w16
162 msubr_q.h $w12, $w21, $w1
[all...] |
| test_mi10.s | 17 # CHECK: ld.w $w12, 1024($13) # encoding: [0x79,0x00,0x6b,0x22]
44 ld.w $w12, 1024($13)
|
| /system/core/libpixelflinger/arch-arm64/ |
| col32cb16blend.S | 57 and w12, w9, w1, lsr #8 // extract green
60 lsl w12, w12, #6 // prescale green
72 madd w7, w7, w5, w12 // dest green * alpha + src green
|
| t32cb16blend.S | 155 // w12: scratch
169 pixel w3, w4, w12, 0
170 strh w12, [x0], #2
187 pixel w3, w4, w12, 0
188 pixel w3, w5, w12, 1
189 str w12, [x0, #-4]
200 pixel w3, w4, w12, 0
201 pixel w3, w5, w12, 1
202 str w12, [x0, #-4]
|
| /external/libhevc/common/arm64/ |
| ihevc_sao_edge_offset_class0.s | 89 LDRB w12,[x11] //pu1_src_top[wd - 1]
97 STRB w12,[x4] //*pu1_src_top_left = pu1_src_top[wd - 1]
125 LDRB w12,[x7] //pu1_avail[0]
126 mov v3.b[0], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
131 mov v3.b[0], w12 //au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
136 LDRB w12,[x7,#1] //pu1_avail[1]
137 mov v3.b[15], w12 //au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
273 LDRB w12,[x7] //pu1_avail[0]
274 mov v3.b[0], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
279 mov v3.b[0], w12 //au1_mask = vsetq_lane_s8(-1, au1_mask, 0
[all...] |
| ihevc_sao_edge_offset_class0_chroma.s | 102 LDRH w12,[x20] //pu1_src_top[wd - 1]
106 STRH w12,[x4] //*pu1_src_top_left = pu1_src_top[wd - 1]
143 LDRB w12,[x7] //pu1_avail[0]
144 mov v3.b[0], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
145 mov v3.b[1], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 1)
150 mov v3.h[0], w12 //au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
155 LDRB w12,[x7,#1] //pu1_avail[1]
156 mov v3.b[14], w12 //au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 14)
157 mov v3.b[15], w12 //au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
330 LDRB w12,[x7] //pu1_avail[0
[all...] |
| ihevc_intra_pred_luma_vert.s | 182 ldrb w12, [x6] //src[2nt+1]
183 sxtw x12,w12
188 dup v24.16b,w12 //src[2nt+1]
189 dup v30.8h,w12
322 ldrb w12, [x6] //src[2nt+1]
323 sxtw x12,w12
328 dup v24.8b,w12 //src[2nt+1]
329 dup v30.8h,w12
|
| ihevc_weighted_pred_bi.s | 154 ldr w12,[sp,#32]
162 sxtw x12,w12
|
| /external/openssh/ |
| blocks.c | 56 M(w3 ,w1 ,w12,w4 ) \
64 M(w11,w9 ,w4 ,w12) \
65 M(w12,w10,w5 ,w13) \
67 M(w14,w12,w7 ,w15) \
118 uint64 w12 = load_bigendian(in + 96); local
135 F(w12,0x72be5d74f27b896fULL)
154 F(w12,0xc6e00bf33da88fc2ULL)
173 F(w12,0xd192e819d6ef5218ULL)
192 F(w12,0x90befffa23631e28ULL)
211 F(w12,0x4cc5d4becb3e42b6ULL
[all...] |
| /external/boringssl/linux-aarch64/crypto/sha/ |
| sha1-armv8.S | 150 add w20,w20,w12 // future e+=X[i]
234 eor w4,w4,w12
309 eor w10,w10,w12
333 eor w12,w12,w14
337 eor w12,w12,w4
341 eor w12,w12,w9
344 ror w12,w12,#3
[all...] |
| sha256-armv8.S | 191 eor w12,w26,w26,ror#14
197 eor w16,w16,w12,ror#11 // Sigma1(e)
198 ror w12,w22,#2
205 eor w17,w12,w17,ror#13 // Sigma0(a)
212 ldp w11,w12,[x1],#2*4
259 rev w12,w12 // 9
268 add w26,w26,w12 // h+=X[i]
438 add w3,w3,w12
478 str w12,[sp,#4
[all...] |
| /external/clang/test/CXX/dcl.dcl/dcl.attr/dcl.align/ |
| p6.cpp | 65 W<1,2> w12; variable
|
| /external/llvm/test/MC/AArch64/ |
| basic-a64-diagnostics.s | 395 cmn w11, w12, lsr #-1
396 cmn w11, w12, lsr #32
412 // CHECK-ERROR-NEXT: cmn w11, w12, lsr #-1
415 // CHECK-ERROR-NEXT: cmn w11, w12, lsr #32
444 cmp w11, w12, lsr #-1
445 cmp w11, w12, lsr #32
461 // CHECK-ERROR-NEXT: cmp w11, w12, lsr #-1
464 // CHECK-ERROR-NEXT: cmp w11, w12, lsr #32
493 neg w11, w12, lsr #-1
494 neg w11, w12, lsr #3
[all...] |
| arm64-arithmetic-encoding.s | 106 add w12, w13, w14
108 add w12, w13, w14, lsl #12
113 ; CHECK: add w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x0b]
115 ; CHECK: add w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x0b]
120 sub w12, w13, w14
122 sub w12, w13, w14, lsl #12
127 ; CHECK: sub w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x4b]
129 ; CHECK: sub w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x4b]
134 adds w12, w13, w14
136 adds w12, w13, w14, lsl #1
[all...] |
| arm64-leaf-compact-unwind.s | 118 ldr w12, [x8]
135 add w9, w9, w12
|
| basic-a64-instructions.s | 629 cmn w12, w13, lsr #0
632 // CHECK: cmn w12, w13, lsr #0 // encoding: [0x9f,0x01,0x4d,0x2b]
[all...] |
| tls-relocs.s | 190 movk w12, #:gottprel_g0_nc:var
194 // CHECK: movk w12, #:gottprel_g0_nc:var // encoding: [0bAAA01100,A,0b100AAAAA,0x72]
|
| /external/v8/test/cctest/ |
| test-disasm-arm64.cc | 270 COMPARE(add(w12, w13, Operand(0xfff000)),
271 "add w12, w13, #0xfff000 (16773120)");
300 COMPARE(sub(w12, w13, Operand(0xfff000)),
301 "sub w12, w13, #0xfff000 (16773120)");
325 COMPARE(add(w12, w13, Operand(w14, LSR, 3)), "add w12, w13, w14, lsr #3");
351 COMPARE(sub(w12, w13, Operand(w14, LSR, 3)), "sub w12, w13, w14, lsr #3");
433 COMPARE(sbc(w12, w13, Operand(w14)), "sbc w12, w13, w14")
[all...] |
| /external/libavc/common/armv8/ |
| ih264_weighted_bi_pred_av8.s | 157 cmp w12, #16
159 cmp w12, #8 //check if wd is 8
435 ldr w12, [sp, #112] //Load wd in x12
437 sxtw x12, w12
442 cmp w12, #8 //check if wd is 8
444 cmp w12, #4 //check if wd is 4
|
