/external/llvm/test/MC/Mips/msa/ |
set-msa-directive.s | 6 # CHECK: addvi.w $w19, $w13, 11 10 # CHECK: subvi.w $w19, $w13, 11 16 addvi.w $w19, $w13, 11 21 subvi.w $w19, $w13, 11
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test_elm_insve.s | 5 # CHECK: insve.w $w0[2], $w13[0] # encoding: [0x79,0x72,0x68,0x19] 10 insve.w $w0[2], $w13[0]
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test_3rf.s | 4 # CHECK: fadd.d $w13, $w2, $w29 # encoding: [0x78,0x3d,0x13,0x5b] 25 # CHECK: fcune.w $w13, $w18, $w19 # encoding: [0x78,0x93,0x93,0x5c] 27 # CHECK: fdiv.w $w13, $w24, $w2 # encoding: [0x78,0xc2,0xc3,0x5b] 30 # CHECK: fexdo.w $w0, $w13, $w27 # encoding: [0x7a,0x3b,0x68,0x1b] 35 # CHECK: fmax.w $w0, $w23, $w13 # encoding: [0x7b,0x8d,0xb8,0x1b] 42 # CHECK: fmin_a.d $w13, $w30, $w24 # encoding: [0x7b,0x78,0xf3,0x5b] 49 # CHECK: fseq.w $w11, $w17, $w13 # encoding: [0x7a,0x8d,0x8a,0xda] 56 # CHECK: fsne.d $w14, $w13, $w23 # encoding: [0x7a,0xf7,0x6b,0x9c] 57 # CHECK: fsor.w $w27, $w13, $w27 # encoding: [0x7a,0x5b,0x6e,0xdc] 63 # CHECK: fsule.w $w23, $w30, $w13 # encoding: [0x7b,0xcd,0xf5,0xda [all...] |
set-msa-directive-bad.s | 11 addvi.w $w19, $w13, 11 # CHECK: error: instruction requires a CPU feature not currently enabled
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test_elm.s | 8 # CHECK: copy_u.w $fp, $w13[2] # encoding: [0x78,0xf2,0x6f,0x99] 15 # CHECK: splati.w $w13, $w18[0] # encoding: [0x78,0x70,0x93,0x59] 24 copy_u.w $30, $w13[2] 31 splati.w $w13, $w18[0]
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test_3r.s | 13 # CHECK: adds_s.w $w16, $w14, $w13 # encoding: [0x79,0x4d,0x74,0x10] 20 # CHECK: addv.h $w4, $w13, $w27 # encoding: [0x78,0x3b,0x69,0x0e] 26 # CHECK: asub_s.d $w13, $w12, $w12 # encoding: [0x7a,0x6c,0x63,0x51] 53 # CHECK: binsl.w $w14, $w15, $w13 # encoding: [0x7b,0x4d,0x7b,0x8d] 62 # CHECK: bneg.d $w13, $w29, $w15 # encoding: [0x7a,0xef,0xeb,0x4d] 83 # CHECK: clt_u.b $w2, $w31, $w13 # encoding: [0x79,0x8d,0xf8,0x8f] 88 # CHECK: div_s.h $w17, $w16, $w13 # encoding: [0x7a,0x2d,0x84,0x52] 98 # CHECK: dotp_u.h $w13, $w2, $w6 # encoding: [0x78,0xa6,0x13,0x53] 120 # CHECK: hsub_s.w $w9, $w13, $w11 # encoding: [0x7b,0x4b,0x6a,0x55] 126 # CHECK: ilvev.h $w14, $w0, $w13 # encoding: [0x7b,0x2d,0x03,0x94 [all...] |
test_2rf.s | 7 # CHECK: fexupr.w $w13, $w4 # encoding: [0x7b,0x32,0x23,0x5e] 13 # CHECK: ffql.w $w31, $w13 # encoding: [0x7b,0x34,0x6f,0xde] 14 # CHECK: ffql.d $w12, $w13 # encoding: [0x7b,0x35,0x6b,0x1e] 40 fexupr.w $w13, $w4 46 ffql.w $w31, $w13 47 ffql.d $w12, $w13
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test_i5.s | 4 # CHECK: addvi.h $w24, $w13, 26 # encoding: [0x78,0x3a,0x6e,0x06] 19 # CHECK: clti_s.b $w19, $w13, -7 # encoding: [0x79,0x19,0x6c,0xc7] 30 # CHECK: maxi_s.d $w13, $w29, -16 # encoding: [0x79,0x70,0xeb,0x46] 49 addvi.h $w24, $w13, 26 64 clti_s.b $w19, $w13, -7 75 maxi_s.d $w13, $w29, -16
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test_mi10.s | 18 # CHECK: ld.w $w13, 2044($14) # encoding: [0x79,0xff,0x73,0x62] 45 ld.w $w13, 2044($14)
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test_bit.s | 27 # CHECK: sat_u.b $w1, $w13, 3 # encoding: [0x78,0xf3,0x68,0x4a] 29 # CHECK: sat_u.w $w31, $w13, 0 # encoding: [0x78,0xc0,0x6f,0xca] 76 sat_u.b $w1, $w13, 3 78 sat_u.w $w31, $w13, 0
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/external/llvm/test/MC/AArch64/ |
arm64-basic-a64-instructions.s | 8 crc32ch w13, w17, w25 16 // CHECK: crc32ch w13, w17, w25 // encoding: [0x2d,0x56,0xd9,0x1a]
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arm64-tls-relocs.s | 82 movz w13, #:tprel_g0:var 87 // CHECK: movz w13, #:tprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12] 206 movz w13, #:dtprel_g0:var 211 // CHECK: movz w13, #:dtprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
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tls-relocs.s | 62 movz w13, #:dtprel_g0:var 69 // CHECK: movz w13, #:dtprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12] 264 movz w13, #:tprel_g0:var 271 // CHECK: movz w13, #:tprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12]
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arm64-arithmetic-encoding.s | 106 add w12, w13, w14 108 add w12, w13, w14, lsl #12 113 ; CHECK: add w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x0b] 115 ; CHECK: add w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x0b] 120 sub w12, w13, w14 122 sub w12, w13, w14, lsl #12 127 ; CHECK: sub w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x4b] 129 ; CHECK: sub w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x4b] 134 adds w12, w13, w14 136 adds w12, w13, w14, lsl #1 [all...] |
arm64-leaf-compact-unwind.s | 119 ldr w13, [x8] 136 add w9, w9, w13
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basic-a64-instructions.s | 55 add x7, x11, w13, uxth #4 59 // CHECK: add x7, x11, w13, uxth #4 // encoding: [0x67,0x31,0x2d,0x8b] 270 add w13, w5, #4095, lsl #12 275 // CHECK: add w13, w5, #4095, lsl #12 // encoding: [0xad,0xfc,0x7f,0x11] 307 adds w13, w23, #291, lsl #12 311 // CHECK: adds w13, w23, #291, lsl #12 // encoding: [0xed,0x8e,0x44,0x31] 370 add w11, w13, w15, lsl #0 374 // CHECK: add w11, w13, w15 // encoding: [0xab,0x01,0x0f,0x0b] 442 adds w11, w13, w15, lsl #0 445 // CHECK: adds w11, w13, w15 // encoding: [0xab,0x01,0x0f,0x2b [all...] |
basic-a64-diagnostics.s | [all...] |
/external/llvm/test/MC/Mips/ |
set-push-pop-directives.s | 11 addvi.b $w15, $w13, 18 27 addvi.b $w15, $w13, 18 34 # CHECK: addvi.b $w15, $w13, 18 53 # CHECK: addvi.b $w15, $w13, 18
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/external/openssh/ |
blocks.c | 57 M(w4 ,w2 ,w13,w5 ) \ 65 M(w12,w10,w5 ,w13) \ 66 M(w13,w11,w6 ,w14) \ 68 M(w15,w13,w8 ,w0 ) 119 uint64 w13 = load_bigendian(in + 104); local 136 F(w13,0x80deb1fe3b1696b1ULL) 155 F(w13,0xd5a79147930aa725ULL) 174 F(w13,0xd69906245565a910ULL) 193 F(w13,0xa4506cebde82bde9ULL) 212 F(w13,0x597f299cfc657e2aULL [all...] |
/external/boringssl/linux-aarch64/crypto/sha/ |
sha1-armv8.S | 164 add w24,w24,w13 // future e+=X[i] 247 eor w5,w5,w13 321 eor w11,w11,w13 345 eor w13,w13,w15 349 eor w13,w13,w5 353 eor w13,w13,w10 356 ror w13,w13,#3 [all...] |
sha256-armv8.S | 216 eor w13,w25,w25,ror#14 222 eor w16,w16,w13,ror#11 // Sigma1(e) 223 ror w13,w21,#2 230 eor w17,w13,w17,ror#13 // Sigma0(a) 261 ldp w13,w14,[x1],#2*4 284 rev w13,w13 // 10 292 add w25,w25,w13 // h+=X[i] 470 add w4,w4,w13 509 str w13,[sp,#8 [all...] |
/bionic/libm/upstream-freebsd/lib/msun/ld128/ |
e_lgammal_r.c | 179 w13 = 2.14830978044410267201172332952040777e+03L, variable 322 y*(w9+y*(w10+y*(w11+y*(w12+y*(w13+y*(w14+y*(w15+y*(w16+
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/external/v8/test/cctest/ |
test-disasm-arm64.cc | 270 COMPARE(add(w12, w13, Operand(0xfff000)), 271 "add w12, w13, #0xfff000 (16773120)"); 300 COMPARE(sub(w12, w13, Operand(0xfff000)), 301 "sub w12, w13, #0xfff000 (16773120)"); 325 COMPARE(add(w12, w13, Operand(w14, LSR, 3)), "add w12, w13, w14, lsr #3"); 351 COMPARE(sub(w12, w13, Operand(w14, LSR, 3)), "sub w12, w13, w14, lsr #3"); 433 COMPARE(sbc(w12, w13, Operand(w14)), "sbc w12, w13, w14") [all...] |
/external/libhevc/common/arm64/ |
ihevc_weighted_pred_bi.s | 155 ldr w13,[sp,#40]
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/external/vixl/test/ |
test-disasm-a64.cc | 271 COMPARE(add(w12, w13, Operand(0xfff000)), 272 "add w12, w13, #0xfff000 (16773120)"); 301 COMPARE(sub(w12, w13, Operand(0xfff000)), 302 "sub w12, w13, #0xfff000 (16773120)"); 325 COMPARE(add(w12, w13, Operand(w14, LSR, 3)), "add w12, w13, w14, lsr #3"); 351 COMPARE(sub(w12, w13, Operand(w14, LSR, 3)), "sub w12, w13, w14, lsr #3"); 433 COMPARE(sbc(w12, w13, Operand(w14)), "sbc w12, w13, w14") [all...] |