| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips5.s | 61 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
74 round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips2.s | 25 round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips3.s | 57 round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid-xfail.s | 14 add.ps $f25,$f27,$f13
221 nmadd.ps $f27,$f4,$f9,$f25
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid-xfail.s | 14 add.ps $f25,$f27,$f13
221 nmadd.ps $f27,$f4,$f9,$f25
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid-xfail.s | 14 add.ps $f25,$f27,$f13
221 nmadd.ps $f27,$f4,$f9,$f25
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid-xfail.s | 14 add.ps $f25,$f27,$f13
223 nmadd.ps $f27,$f4,$f9,$f25
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid-xfail.s | 14 add.ps $f25,$f27,$f13
223 nmadd.ps $f27,$f4,$f9,$f25
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid-xfail.s | 14 add.ps $f25,$f27,$f13
223 nmadd.ps $f27,$f4,$f9,$f25
|
| /external/libunwind/src/ia64/ |
| getcontext.S | 162 stf.spill [r8] = f27, (FR(29) - FR(27)) // M3
|
| /external/llvm/test/CodeGen/SPARC/ |
| float.ll | 76 tail call void asm sideeffect "", "~{f0},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
|
| fp128.ll | 60 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips64.s | 30 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/v8/src/mips/ |
| constants-mips.cc | 85 "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
|
| /external/v8/src/mips64/ |
| constants-mips64.cc | 85 "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
|
| /external/llvm/test/MC/Disassembler/Mips/mips3/ |
| valid-mips3-el.txt | 113 0x00 0xd8 0x07 0x44 # CHECK: mfc1 $7, $f27
118 0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
142 0xcc 0xe6 0x00 0x46 # CHECK: round.w.s $f27, $f28
|
| valid-mips3.txt | 113 0x44 0x07 0xd8 0x00 # CHECK: mfc1 $7, $f27
118 0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27
142 0x46 0x00 0xe6 0xcc # CHECK: round.w.s $f27, $f28
|
| /external/google-breakpad/src/common/ |
| dwarf_cfi_to_module.cc | 137 "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27",
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 38 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/CodeGen/SystemZ/ |
| risbg-01.ll | 308 define i64 @f27(i64 %foo) {
309 ; CHECK-LABEL: f27:
|
| /external/valgrind/memcheck/ |
| mc_machine.c | [all...] |
| /external/valgrind/memcheck/tests/ |
| deep-backtrace.c | 27 int f27(int *p) { return f26(p); } function
28 int f28(int *p) { return f27(p); }
|
| /external/elfutils/src/tests/ |
| run-allregs.sh | 218 59: f27 (f27), float 64 bits
[all...] |
| /external/libcxxabi/src/Unwind/ |
| UnwindRegistersRestore.S | 168 lfd f27,376(r3)
|
| UnwindRegistersSave.S | 172 stfd f27,376(r3)
|
