| /bionic/libc/arch-mips/bionic/ |
| setjmp.S | 153 #define SC_FPREGS_SAVED 8 /* all fp regs f24,f25,f26,f27,f28,f29,f30,f31 */
231 s.d $f27, SC_FPREGS+3*REGSZ_FP(a0)
329 l.d $f27, SC_FPREGS+3*REGSZ_FP(a0)
|
| /external/llvm/test/MC/Disassembler/Mips/mips2/ |
| valid-mips2-el.txt | 69 0x00 0xd8 0x07 0x44 # CHECK: mfc1 $7, $f27
74 0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
96 0xcc 0xe6 0x00 0x46 # CHECK: round.w.s $f27, $f28
|
| valid-mips2.txt | 69 0x44 0x07 0xd8 0x00 # CHECK: mfc1 $7, $f27
74 0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27
96 0x46 0x00 0xe6 0xcc # CHECK: round.w.s $f27, $f28
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 84 div.d $f29,$f20,$f27
170 mfc1 $a3,$f27
176 mov.s $f2,$f27
185 movn.d $f27,$f21,$k0
211 neg.d $f27,$f18
233 round.w.s $f27,$f28
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 84 div.d $f29,$f20,$f27
170 mfc1 $a3,$f27
176 mov.s $f2,$f27
185 movn.d $f27,$f21,$k0
211 neg.d $f27,$f18
233 round.w.s $f27,$f28
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 84 div.d $f29,$f20,$f27
170 mfc1 $a3,$f27
176 mov.s $f2,$f27
185 movn.d $f27,$f21,$k0
211 neg.d $f27,$f18
233 round.w.s $f27,$f28
|
| /external/clang/test/CodeGen/ |
| mips-clobber-reg.c | 112 __asm__ __volatile__ ("fadd.s $f27,77":::"$f27");
|
| x86_32-arguments-darwin.c | 119 // CHECK: void @f27(%struct.s27* noalias sret %agg.result)
121 struct s27 { struct { char a, b, c; } a; struct { char a; } b; } f27(void) { while (1) {} } function
|
| x86_64-arguments.c | 182 struct v4f32wrapper f27(struct v4f32wrapper X) { function
183 // CHECK-LABEL: define <4 x float> @f27(<4 x float> %X.coerce)
|
| /external/llvm/test/CodeGen/SystemZ/ |
| int-const-02.ll | 223 define i64 @f27() {
224 ; CHECK-LABEL: f27:
|
| memcpy-02.ll | 324 define void @f27(i64 *%ptr) {
325 ; CHECK-LABEL: f27:
|
| memset-03.ll | 255 define void @f27(i8 *%dest) {
256 ; CHECK-LABEL: f27:
|
| memset-04.ll | 259 define void @f27(i8 *%dest) {
260 ; CHECK-LABEL: f27:
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64-xfail.txt | 32 0x46 0xcd 0xde 0x40 # CHECK: add.ps $f25, $f27, $f13
67 0x4c 0x99 0x4e 0xf6 # CHECK: nmadd.ps $f27, $f4, $f9, $f25
|
| /art/compiler/optimizing/ |
| code_generator_mips64.h | 61 { F24, F25, F26, F27, F28, F29, F30, F31 };
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| valid-mips4-el.txt | 118 0x00 0xd8 0x07 0x44 # CHECK: mfc1 $7, $f27
123 0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
130 0xd3 0xae 0x3a 0x46 # CHECK: movn.d $f27, $f21, $26
160 0xcc 0xe6 0x00 0x46 # CHECK: round.w.s $f27, $f28
|
| valid-mips4.txt | 118 0x44 0x07 0xd8 0x00 # CHECK: mfc1 $7, $f27
123 0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27
130 0x46 0x3a 0xae 0xd3 # CHECK: movn.d $f27, $f21, $26
160 0x46 0x00 0xe6 0xcc # CHECK: round.w.s $f27, $f28
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32.s | 29 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips4.s | 19 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 20 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/mesa3d/src/mesa/sparc/ |
| sparc_matrix.h | 46 #define M11 %f27
|
| /external/libunwind/src/ia64/ |
| Ginstall_cursor.S | 124 ldf.fill f27 = [r27] // f27 restored (don't touch no more)
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| PPCDisassembler.cpp | 79 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
121 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
|
| /external/llvm/test/MC/Disassembler/Mips/mips1/ |
| valid-mips1-el.txt | 55 0x00 0xd8 0x07 0x44 # CHECK: mfc1 $7, $f27
60 0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
|
| valid-mips1.txt | 55 0x44 0x07 0xd8 0x00 # CHECK: mfc1 $7, $f27
60 0x46 0x00 0xd8 0x86 # CHECK: mov.s $f2, $f27
|
