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  /prebuilts/tools/common/proguard/proguard4.7/lib/
proguard.jar 
  /art/compiler/optimizing/
register_allocator.h 114 HInstruction* instruction,
118 HInstruction* instruction,
121 void InsertMoveAfter(HInstruction* instruction, Location source, Location destination) const;
127 HInstruction* instruction,
134 HInstruction* instruction,
139 void ProcessInstruction(HInstruction* instruction);
187 // where an instruction requires a specific register.
192 // where an instruction requires a temporary.
  /art/disassembler/
disassembler.h 61 // Dump a single instruction returning the length of that instruction.
  /art/runtime/arch/arm64/
fault_handler_arm64.cc 79 // Work out the return PC. This will be the address of the instruction
80 // following the faulting ldr/str instruction.
91 // the load/store instruction that might cause the fault.
103 // A suspend check is done using the following instruction sequence:
127 // Second instruction is not good, not ours.
131 // The first instruction can a little bit up the stream due to load hoisting
148 // will resume the instruction (current PC + 4). PC points to the
149 // ldr x0,[x0,#0] instruction (r0 will be 0, set by the trigger).
  /art/test/471-deopt-environment/src/
Main.java 30 // 3) Instruction simplifier simpilifying the inlined willInline to just `field`.
32 // At this point, if the environment of the HDeoptimization instruction was
  /art/test/513-array-deopt/src/
Main.java 23 // The next instruction will record that the lower bound is 5.
35 // The next instruction will record that the lower bound is 1.
  /art/tools/dexfuzz/src/dexfuzz/rawdex/formats/
Format20bc.java 20 import dexfuzz.rawdex.Instruction;
30 public void writeToFile(DexRandomAccessFile file, Instruction insn) throws IOException {
  /dalvik/dexgen/src/com/android/dexgen/dex/code/
OddSpacer.java 24 * Pseudo-instruction which either turns into a {@code nop} or
25 * nothingness, in order to make the subsequent instruction have an
  /dalvik/dexgen/src/com/android/dexgen/dex/code/form/
Form10x.java 25 * Instruction format {@code 10x}. See the instruction format spec
Form30t.java 25 * Instruction format {@code 30t}. See the instruction format spec
  /dalvik/dx/src/com/android/dx/dex/code/
OddSpacer.java 25 * Pseudo-instruction which either turns into a {@code nop} or
26 * nothingness, in order to make the subsequent instruction have an
  /dalvik/dx/src/com/android/dx/dex/code/form/
Form10x.java 25 * Instruction format {@code 10x}. See the instruction format spec
Form30t.java 25 * Instruction format {@code 30t}. See the instruction format spec
SpecialFormat.java 24 * Instruction format for nonstandard format instructions, which aren't
25 * generally real instructions but do end up appearing in instruction
  /external/dexmaker/src/dx/java/com/android/dx/dex/code/
OddSpacer.java 25 * Pseudo-instruction which either turns into a {@code nop} or
26 * nothingness, in order to make the subsequent instruction have an
  /external/dexmaker/src/dx/java/com/android/dx/dex/code/form/
Form10x.java 25 * Instruction format {@code 10x}. See the instruction format spec
Form30t.java 25 * Instruction format {@code 30t}. See the instruction format spec
SpecialFormat.java 24 * Instruction format for nonstandard format instructions, which aren't
25 * generally real instructions but do end up appearing in instruction
  /external/iptables/extensions/
libxt_bpf.man 9 instruction. Instruction lines follow the pattern 'u16 u8 u8 u32' in decimal
  /external/kernel-headers/original/uapi/asm-arm/asm/
swab.h 7 * and word accesses (data or instruction) appear as:
12 * and word accesses (data or instruction) appear as:
  /external/llvm/docs/HistoricalNotes/
2001-07-06-LoweringIRForCodeGen.txt 8 move-conditional instruction. I don't think we want to put that in the core
10 conditional move instruction in the VM, it is pretty difficult to maintain a
  /external/llvm/lib/Transforms/Instrumentation/
BoundsChecking.cpp 59 Instruction *Inst;
95 /// emitBranchToTrap - emit a branch instruction to a trap block.
109 Instruction *Inst = Builder->GetInsertPoint();
177 // check HANDLE_MEMORY_INST in include/llvm/Instruction.def for memory
179 std::vector<Instruction*> WorkList;
181 Instruction *I = &*i;
188 for (std::vector<Instruction*>::iterator i = WorkList.begin(),
205 llvm_unreachable("unknown Instruction type");
  /external/llvm/test/CodeGen/AArch64/
regress-tblgen-chains.ll 4 ; instruction as needing a chain on its own account if it had a built-in pattern
7 ; LS8_LDR instruction (same operands other than the non-existent chain) and the
  /external/llvm/test/CodeGen/X86/
misched-aa-mmos.ll 3 ; This generates a decw instruction, which has two MMOs, and an alias SU edge
4 ; query involving that instruction. Make sure this does not crash.
  /external/llvm/test/MC/ARM/
directive-arch_extension-sec.s 20 @ CHECK-V6: error: instruction requires: TrustZone
30 @ CHECK-V7: error: instruction requires: TrustZone

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