| /external/smali/dexlib2/src/test/java/org/jf/dexlib2/builder/ |
| FixOffsetsTest.java | 37 import org.jf.dexlib2.builder.instruction.BuilderInstruction10t;
38 import org.jf.dexlib2.builder.instruction.BuilderInstruction10x;
44 import org.jf.dexlib2.iface.instruction.Instruction;
45 import org.jf.dexlib2.iface.instruction.OffsetInstruction;
101 List<? extends Instruction> instructions = Lists.newArrayList(impl.getInstructions());
|
| /external/vixl/src/vixl/a64/ |
| cpu-a64.cc | 112 // instruction and data caches are guaranteed to see the same copy of a
125 // instruction cache operations (below).
131 // the point by which the instruction and data caches of all the processors
142 // ic : Instruction Cache maintenance
154 // Make sure that the instruction cache operations (above) take effect
160 // isb : Instruction Synchronisation Barrier
|
| /frameworks/compile/mclinker/lib/Target/AArch64/ |
| AArch64PLT.cpp | 83 // apply 2nd instruction
91 // apply 3rd instruction
94 // apply 4th instruction
126 // apply 1st instruction
130 // apply 2nd instruction
133 // apply 3rd instruction
|
| /external/v8/src/arm/ |
| simulator-arm.cc | 38 void Stop(Instruction* instr);
56 bool SetBreakpoint(Instruction* breakpc);
57 bool DeleteBreakpoint(Instruction* breakpc);
83 void ArmDebugger::Stop(Instruction* instr) {
88 reinterpret_cast<char**>(sim_->get_pc() + Instruction::kInstrSize);
102 // Overwrite the instruction and address with nops.
104 reinterpret_cast<Instruction*>(msg_address)->SetInstructionBits(kNopInstr);
106 sim_->set_pc(sim_->get_pc() + 2 * Instruction::kInstrSize);
115 void ArmDebugger::Stop(Instruction* instr) {
120 + Instruction::kInstrSize)
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| IntegerDivision.cpp | 31 /// instruction. This will generate a urem in the process, and Builder's insert
68 if (Instruction *URemInst = dyn_cast<Instruction>(URem))
77 /// code generated, e.g. at the urem instruction. This will generate a udiv in
93 if (Instruction *UDiv = dyn_cast<Instruction>(Quotient))
101 /// code generated, e.g. at the sdiv instruction. This will generate a udiv in
142 if (Instruction *UDiv = dyn_cast<Instruction>(Q_Mag))
150 /// point where the caller wants code generated, e.g. at the udiv instruction
[all...] |
| /external/llvm/test/MC/AArch64/ |
| basic-a64-diagnostics.s | 43 // CHECK-ERROR: error: invalid operand for instruction
55 // CHECK-ERROR: error: invalid operand for instruction
119 // CHECK-ERROR: error: invalid operand for instruction
122 // CHECK-ERROR-NEXT: error: invalid operand for instruction
125 // CHECK-ERROR-NEXT: error: invalid operand for instruction
128 // CHECK-ERROR-NEXT: error: invalid operand for instruction
135 // CHECK-ERROR: error: invalid operand for instruction
138 // CHECK-ERROR-NEXT: error: invalid operand for instruction
153 // CHECK-ERROR: error: invalid operand for instruction
156 // CHECK-ERROR-NEXT: error: invalid operand for instruction
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineLoadStoreAlloca.cpp | 38 if (CE->getOpcode() == Instruction::BitCast ||
39 CE->getOpcode() == Instruction::AddrSpaceCast ||
40 CE->getOpcode() == Instruction::GetElementPtr)
55 SmallVectorImpl<Instruction *> &ToDelete) {
66 Instruction *I = cast<Instruction>(U.getUser());
148 // Otherwise, the transform is safe. Remember the copy instruction.
160 SmallVectorImpl<Instruction *> &ToDelete) {
167 static Instruction *simplifyAllocaArraySize(InstCombiner &IC, AllocaInst &AI) {
194 // insert our getelementptr instruction..
[all...] |
| /dalvik/dx/src/com/android/dx/dex/code/ |
| DalvInsn.java | 49 * Makes a move instruction, appropriate and ideal for the given arguments.
83 * <p><b>Note:</b> In the unlikely event that an instruction takes
146 * Gets whether the address of this instruction is known.
156 * Gets the output address of this instruction, if it is known. This throws
190 * Gets the register list for this instruction.
210 * Gets the minimum distinct registers required for this instruction.
241 * Gets the instruction that is equivalent to this one, except that
254 * Gets the instruction prefix required, if any, to use in an expanded
279 * Gets the instruction suffix required, if any, to use in an expanded
298 * Gets the instruction that is equivalent to this one, except tha
[all...] |
| RopTranslator.java | 135 * objects per basic block (to the first and last instruction,
144 * extra instruction per block (for the locals state at the
258 * Choose and append an output instruction for each original
259 * instruction.
445 * given rop instruction. For insns that are commutative, have
449 * @param insn {@code non-null;} instruction in question
450 * @return {@code non-null;} the instruction's complete register list
458 * given rop instruction. For insns that are commutative, have
462 * @param insn {@code non-null;} instruction in question
464 * @return {@code non-null;} the instruction's complete register lis
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| DalvInsn.java | 48 * Makes a move instruction, appropriate and ideal for the given arguments.
82 * <p><b>Note:</b> In the unlikely event that an instruction takes
145 * Gets whether the address of this instruction is known.
155 * Gets the output address of this instruction, if it is known. This throws
189 * Gets the register list for this instruction.
209 * Gets the minimum distinct registers required for this instruction.
240 * Gets the instruction that is equivalent to this one, except that
253 * Gets the instruction prefix required, if any, to use in an expanded
278 * Gets the instruction suffix required, if any, to use in an expanded
297 * Gets the instruction that is equivalent to this one, except tha
[all...] |
| /external/llvm/lib/IR/ |
| Dominators.cpp | 81 bool DominatorTree::dominates(const Instruction *Def,
82 const Instruction *User) const {
94 // An instruction doesn't dominate a use in itself.
98 // The value defined by an invoke dominates an instruction only if
99 // it dominates every instruction in UseBB.
100 // A PHI is dominated only if the instruction dominates every possible use
116 // true if Def would dominate a use in any instruction in UseBB.
118 bool DominatorTree::dominates(const Instruction *Def,
201 Instruction *UserInst = cast<Instruction>(U.getUser())
[all...] |
| /external/valgrind/exp-bbv/docs/ |
| bbv-manual.xml | 147 instead of just instruction counts. The
183 This option tells the tool to only display instruction count
185 This is useful for debugging, and for gathering instruction count
277 Then each native instruction in the block is instrumented to
278 call an instruction counting routine with a pointer to the block
283 At run-time, our instruction counting routines are called once
284 per native instruction. The relevant block info structure is accessed
285 and the block count and total instruction count is updated.
286 If the total instruction count overflows the interval size
295 actual hardware counts a rep-prefixed instruction
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetSchedule.td | 14 // 1. Basic properties for coarse grained instruction cost model.
16 // 3. Instruction itineraties for detailed reservation tables.
26 // modifying the Instruction definition to inherit from Sched. For
30 // B. In each instruction definition, name an ItineraryClass. For each
38 // ItineraryClasses defined by the Instruction. As in method B, the
45 // an instruction's machine model via custom C++ code. It also allows
53 // Include legacy support for instruction itineraries.
56 class Instruction; // Forward def
58 // DAG operator that interprets the DAG args as Instruction defs.
62 // matching Instruction opcode names
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
173 /// such, whenever a client has an instance of instruction info, it should
179 /// this instruction. For x86, we need to handle more complex call
183 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
184 /// extension instruction. That is, it's like a copy where it's legal for the
217 /// into the right format for a particular kind of LEA instruction. This may
223 /// operand to the LEA instruction.
231 /// may be able to convert a two-address instruction into a true
232 /// three-address instruction on demand. This allows the X86 target (for
237 /// performed, otherwise it returns the new instruction
[all...] |
| X86VZeroUpper.cpp | 1 //===-- X86VZeroUpper.cpp - AVX vzeroupper instruction inserter -----------===//
57 // - EXITS_CLEAN: There is (or will be) a vzeroupper instruction in this
59 // - EXITS_DIRTY: An instruction in the block dirties YMM and no
141 /// instruction.
156 // Insert a vzeroupper instruction before I.
191 // We found a ymm-using instruction; this could be an AVX instruction,
210 // The VZEROUPPER instruction resets the upper 128 bits of all Intel AVX
211 // registers. This instruction has zero latency. In addition, the processor
214 // the VZEROUPPER instruction before any function call/return that migh
[all...] |
| /dalvik/dx/src/com/android/dx/ssa/ |
| EscapeAnalysis.java | 136 * Finds the corresponding instruction for a given move result
138 * @param moveInsn {@code non-null;} a move result instruction
139 * @return {@code non-null;} the instruction that produces the result for
149 * Finds the corresponding move result for a given instruction
151 * @param insn {@code non-null;} an instruction that must always be
153 * @return {@code non-null;} the move result for the given instruction
163 * instruction. The object being put is the child and the object being put
212 * Process a single instruction, looking for new objects resulting from
215 * @param insn {@code non-null;} instruction to process
244 * Determine the origin of a move result pseudo instruction that generate
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| EscapeAnalysis.java | 137 * Finds the corresponding instruction for a given move result
139 * @param moveInsn {@code non-null;} a move result instruction
140 * @return {@code non-null;} the instruction that produces the result for
150 * Finds the corresponding move result for a given instruction
152 * @param insn {@code non-null;} an instruction that must always be
154 * @return {@code non-null;} the move result for the given instruction
164 * instruction. The object being put is the child and the object being put
213 * Process a single instruction, looking for new objects resulting from
216 * @param insn {@code non-null;} instruction to process
245 * Determine the origin of a move result pseudo instruction that generate
[all...] |
| /external/v8/src/mips64/ |
| constants-mips64.h | 17 #define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n")
81 // Volume II: The MIPS32 Instruction Set
133 // 'pref' instruction hints
256 // Instruction bit masks.
277 // MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set.
740 // A nop instruction. (Encoding of sll 0 0 0).
743 class Instruction {
749 // always the value of the current instruction being executed.
753 // Get the raw instruction bits.
758 // Set the raw instruction bits to value
[all...] |
| /art/compiler/dex/quick/mips/ |
| codegen_mips.h | 73 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
142 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
144 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
150 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
152 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
154 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
156 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
158 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
167 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
279 void GenDivRemLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1
[all...] |
| /external/llvm/lib/Analysis/ |
| LazyValueInfo.cpp | 368 Instruction *CxtI = nullptr);
380 Instruction *BBI, BasicBlock *BB);
382 Instruction *BBI);
394 Instruction *CxtI = nullptr);
397 /// value for the specified Value* at the specified instruction (generally
399 LVILatticeVal getValueAt(Value *V, Instruction *CxtI);
404 Instruction *CxtI = nullptr);
520 Instruction *BBI = dyn_cast<Instruction>(Val);
571 static bool InstructionDereferencesPointer(Instruction *I, Value *Ptr)
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DbgValueHistoryCalculator.cpp | 38 // Instruction range should start with a DBG_VALUE instruction for the
54 // Verify that the current instruction range is not yet closed.
56 // For now, instruction ranges are not allowed to cross basic block
108 // instruction to their history, clobbering it.
145 // \brief Returns the first instruction in @MBB which corresponds to
151 // Assume that epilogue starts with instruction having the same debug location
152 // as the return instruction.
194 // Not a DBG_VALUE instruction. It may clobber registers which describe
203 assert(MI.getNumOperands() > 1 && "Invalid DBG_VALUE instruction!");
[all...] |
| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 83 // Set up the instruction printer.
167 // Get the scheduling class of the requested instruction.
194 // Get the scheduling class of the requested instruction.
230 // LLVMDisasmInstruction() disassembles a single instruction using the
232 // instruction are specified in the parameter Bytes, and contains at least
233 // BytesSize number of bytes. The instruction is at the address specified by
234 // the PC parameter. If a valid instruction can be disassembled its string is
237 // instruction or zero if there was no valid instruction. If this function
310 // Try to set up the new instruction printer
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64A53Fix835769.cpp | 10 // It works around it by inserting a nop instruction in code sequences that
12 // It inserts a nop instruction between a sequence of the following 2 classes
39 // Is the instruction a match for the instruction that comes first in the
42 // Must return true if this instruction is a load, a store or a prefetch.
55 // Is the instruction a match for the instruction that comes second in the
166 // If we are the first instruction of the block, put the NOP at the end of
170 assert(I && "Expected instruction");
195 // Try and find the last non-pseudo instruction in any fallen through blocks
[all...] |
| /external/llvm/lib/Transforms/ObjCARC/ |
| DependencyAnalysis.cpp | 33 /// Test whether the given instruction can result in a reference count
35 bool llvm::objcarc::CanAlterRefCount(const Instruction *Inst, const Value *Ptr,
71 bool llvm::objcarc::CanDecrementRefCount(const Instruction *Inst,
83 /// Test whether the given instruction can "use" the given pointer's object in a
85 bool llvm::objcarc::CanUse(const Instruction *Inst, const Value *Ptr,
135 llvm::objcarc::Depends(DependenceKind Flavor, Instruction *Inst,
225 BasicBlock *StartBB, Instruction *StartInst,
226 SmallPtrSetImpl<Instruction *> &DependingInsts,
255 Instruction *Inst = --LocalStartPos;
273 DependingInsts.insert(reinterpret_cast<Instruction *>(-1))
[all...] |
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_info.c | 176 * Process an instruction, and update the register values accordingly.
189 for (i = 0; i < inst->Instruction.NumDstRegs; ++i) {
215 switch (inst->Instruction.Opcode) {
260 if (!inst->Instruction.Predicate &&
261 !inst->Instruction.Saturate) {
264 if (inst->Instruction.Opcode == TGSI_OPCODE_MOV) {
267 } else if (inst->Instruction.Opcode == TGSI_OPCODE_MUL) {
304 switch (inst->Instruction.Opcode) {
428 if (inst->Instruction.Opcode == TGSI_OPCODE_END ||
429 inst->Instruction.Opcode == TGSI_OPCODE_BGNSUB)
[all...] |
