| /external/llvm/include/llvm/CodeGen/ |
| RegisterPressure.h | 219 /// Track the current register pressure at some position in the instruction
255 /// Register pressure corresponds to liveness before this instruction
257 /// an instruction.
301 /// \brief Get the SlotIndex for the first nondebug instruction including or
305 /// Recede across the previous instruction.
309 /// Advance across the current instruction.
345 /// Consider the pressure increase caused by traversing this instruction
348 /// excess register units of that pressure set introduced by this instruction.
361 /// Consider the pressure increase caused by traversing this instruction
364 /// excess register units of that pressure set introduced by this instruction
[all...] |
| SelectionDAGISel.h | 11 // base class for SelectionDAG-based instruction selectors.
41 /// pattern-matching instruction selectors.
72 /// instruction selection starts.
85 /// (which will appear in the machine instruction) should be added to the
94 /// operand node N of U during instruction selection that starts at Root.
98 /// U can be folded during instruction selection that starts at Root.
177 /// DAGSize - Size of DAG being instruction selected.
265 /// \brief Perform instruction selection on all basic blocks in the function.
268 /// \brief Perform instruction selection on a single basic block, for
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVLIWPacketizer.cpp | 11 // machine basic blocks. For each instruction I in BB, the packetizer consults
13 // packetizer checks if I depends on any instruction J in the current packet.
95 // Has the instruction been promoted to a dot-new instruction.
98 // Has the instruction been glued to allocframe.
101 // Has the feeder instruction been glued to new value jump.
104 // Check if there is a dependence between some instruction already in this
105 // packet and this instruction.
109 // schedule this instruction.
130 // isSoloInstruction - return true if instruction MI can not be packetize
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| /external/llvm/utils/TableGen/ |
| DFAPacketizerEmitter.cpp | 11 // to reason about whether an instruction can be added to a packet on a VLIW
62 // a set of instruction classes.
69 // with three instruction classes: L, M, and L_or_M.
70 // From the initial state (currentState = 0x00), if we add instruction class
73 // instruction
100 // canAddInsnClass - Returns true if an instruction of type InsnClass is a
101 // valid transition from this state, i.e., can an instruction of type InsnClass
227 // canAddInsnClass - Quickly verifies if an instruction of type InsnClass is a
228 // valid transition from this state i.e., can an instruction of type InsnClass
401 // Collect the instruction classes
[all...] |
| /external/proguard/src/proguard/optimize/peephole/ |
| MethodInliner.java | 29 import proguard.classfile.instruction.*;
30 import proguard.classfile.instruction.visitor.InstructionVisitor;
357 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction)
359 codeAttributeComposer.appendInstruction(offset, instruction);
365 // Are we inlining this instruction?
377 // Are we not at the last instruction?
380 // Replace the return instruction by a branch instruction.
381 Instruction branchInstruction
[all...] |
| /external/v8/src/ |
| lithium-allocator.h | 35 // For each lithium instruction there are exactly two lifetime positions:
36 // the beginning and the end of the instruction. Lifetime positions for
41 // the instruction with the given index.
51 // Returns the index of the instruction to which this lifetime position
58 // Returns true if this lifetime position corresponds to the instruction
64 // Returns the lifetime position for the start of the instruction which
71 // Returns the lifetime position for the end of the instruction which
78 // Returns the lifetime position for the beginning of the next instruction.
85 // instruction.
93 // instruction
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| BasicBlockList.java | 102 * Gets the total instruction count for this instance. This is the
103 * sum of the instruction counts of each block.
105 * @return {@code >= 0;} the total instruction count
122 * Gets the total instruction count for this instance, ignoring
125 * @return {@code >= 0;} the total instruction count
170 * Visits each instruction of each block in the list, in order.
186 * the registers in each instruction are offset by the given
312 * Instruction visitor class for counting registers used.
368 * @param insn {@code non-null;} instruction being visited
|
| /dalvik/dx/src/com/android/dx/cf/code/ |
| BytecodeArray.java | 101 * Parses each instruction in the array, in order.
104 * each instruction
120 * Finds the offset to each instruction in the bytecode array. The
142 * in the set, clearing it, and parsing and visiting the instruction at
149 * each instruction
168 * Parses the instruction at the indicated offset. Indicate the
170 * number of bytes consumed by the instruction.
213 * instruction
215 * @return the length of the instruction, in bytes
[all...] |
| /dalvik/dx/src/com/android/dx/rop/code/ |
| BasicBlockList.java | 102 * Gets the total instruction count for this instance. This is the
103 * sum of the instruction counts of each block.
105 * @return {@code >= 0;} the total instruction count
122 * Gets the total instruction count for this instance, ignoring
125 * @return {@code >= 0;} the total instruction count
169 * Visits each instruction of each block in the list, in order.
185 * the registers in each instruction are offset by the given
310 * Instruction visitor class for counting registers used.
366 * @param insn {@code non-null;} instruction being visited
|
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| BasicBlockList.java | 102 * Gets the total instruction count for this instance. This is the
103 * sum of the instruction counts of each block.
105 * @return {@code >= 0;} the total instruction count
122 * Gets the total instruction count for this instance, ignoring
125 * @return {@code >= 0;} the total instruction count
169 * Visits each instruction of each block in the list, in order.
185 * the registers in each instruction are offset by the given
310 * Instruction visitor class for counting registers used.
366 * @param insn {@code non-null;} instruction being visited
|
| /external/google-breakpad/src/processor/ |
| stackwalker_amd64.cc | 118 // The instruction pointer is stored directly in a register, so pull it
123 frame->instruction = frame->context.rip;
161 // With this assumption, the CALL instruction pushes the return address
287 // Treat an instruction address of 0 as end-of-stack.
297 // new_frame->context.rip is the return address, which is the instruction
299 // new_frame->instruction to one less than that, so it points within the
300 // CALL instruction. See StackFrame::instruction for details, and
302 new_frame->instruction = new_frame->context.rip - 1;
|
| basic_source_line_resolver_unittest.cc | 187 frame.instruction = 0x1000;
214 frame.instruction = 0x800;
221 frame.instruction = 0x1280;
232 frame.instruction = 0x1380;
243 frame.instruction = 0x2000;
250 frame.instruction = 0x3d3f;
255 frame.instruction = 0x3e9f;
265 // Regardless of which instruction evaluation takes place at, it
274 frame.instruction = 0x3d40;
290 frame.instruction = 0x3d41
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 37 "Unpack machine instruction bundles", false, false)
48 // Remove BUNDLE instruction and the InsideBundle flags from bundled
88 "Finalize machine instruction bundles", false, false)
95 /// finalizeBundle - Finalize a machine instruction bundle which includes
97 /// This routine adds a BUNDLE instruction to represent the bundle, it adds
100 /// instruction.
207 /// the last instruction in the bundle is not provided as an input. This is
209 /// with 'InsideBundle' marker. It returns the MBB instruction iterator that
222 /// finalizeBundles - Finalize instruction bundles in the specified
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
44 /// such, whenever a client has an instance of instruction info, it should
72 /// \brief Does this instruction set its full destination register to zero?
75 /// \brief Does this instruction rename a GPR without modifying bits?
78 /// \brief Does this instruction rename an FPR without modifying bits?
156 /// analyzeCompare - For a comparison instruction, return the source registers
158 /// Return true if the comparison instruction can be analyzed.
162 /// optimizeCompareInstr - Convert the instruction supplying the argument to
169 /// for an instruction chain ending in <Root>. All potential patterns are
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
49 /// instruction.
169 /// specified Branch instruction.
204 // Get the second to last instruction in the block.
217 // If there is only one terminator instruction, process it.
237 // If second to last instruction is an unconditional branch,
238 // analyze it and remove the last instruction.
240 // Return if the last instruction cannot be removed.
261 /// Return the number of bytes of code the specified instruction may be.
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 47 /// instruction info tracks.
221 // Instruction encodings. These are the standard/most common forms for X86
225 // PseudoFrm - This represents an instruction that is a pseudo instruction
275 /// RawFrmImm8 - This is used for the ENTER instruction, which has two
326 // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
327 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
328 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
337 // AsSize - AdSizeX implies this instruction determines its need of 0x67
366 // OpMap - This field determines which opcode map this instruction
[all...] |
| /external/llvm/lib/Transforms/IPO/ |
| IPConstantPropagation.cpp | 95 // Used by a non-instruction, or not the callee of a function, do not
100 CallSite CS(cast<Instruction>(UR));
226 Instruction* Call = CS.getInstruction();
228 // Not a call instruction or a call instruction that's not calling F
243 // the call instruction and use that.
250 Instruction *Ins = cast<Instruction>(*I);
268 // the call instruction and use that.
|
| /external/llvm/lib/Transforms/Scalar/ |
| SCCP.cpp | 71 /// overdefined - This instruction is not known to be constant, and we know
305 // is not already a constant, add it to the instruction work list so that
306 // the users of the instruction are updated later.
335 // value is not already overdefined, add it to the overdefined instruction
336 // work list so that the users of the instruction are updated later.
442 // successors are reachable from a given terminator instruction.
452 // instruction that was just changed state somehow. Based on this
453 // information, we need to update the specified user of this instruction.
455 void OperandChangedState(Instruction *I) {
463 // visit implementations - Something changed in this instruction. Either a
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_wm_pass0.c | 56 /** return pointer to a newly allocated instruction */
60 memset(&c->instruction[c->nr_insns], 0, sizeof(*c->instruction));
61 return &c->instruction[c->nr_insns++];
241 * Straight translation to internal instruction format
295 newref->insn = insn - c->instruction;
321 /* Copy some data out of the instruction
406 * an instruction produces duplicate values (eg DP3), all are given
424 /* Optimize away moves, otherwise emit translated instruction:
|
| /external/valgrind/none/tests/mips32/ |
| MoveIns.c | 25 #define TESTINSNMOVE(instruction, offset, FS, RT) \
32 instruction "\n\t" \
40 instruction, out, out1); \
44 #define TESTINSNMOVEd(instruction, offset, FS, RT) \
51 instruction "\n\t" \
59 instruction, out, out1); \
63 #define TESTINSNMOVEt(instruction, offset, FS, RT) \
70 instruction "\n\t" \
78 instruction, out, out1); \
82 #define TESTINSNMOVEtd(instruction, offset, FS, RT)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 135 bool fastSelectInstruction(const Instruction *I) override;
144 // Instruction selection routines.
146 bool SelectLoad(const Instruction *I);
147 bool SelectStore(const Instruction *I);
148 bool SelectBranch(const Instruction *I);
149 bool SelectIndirectBr(const Instruction *I);
150 bool SelectCmp(const Instruction *I);
151 bool SelectFPExt(const Instruction *I);
152 bool SelectFPTrunc(const Instruction *I);
153 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode)
[all...] |
| /dalvik/dx/src/com/android/dx/ssa/ |
| DeadCodeRemover.java | 139 // Delete this instruction completely if it has sources
144 // Delete this instruction from all usage lists.
150 // Remove this instruction result from the sources of any phis
209 * @param insn {@code null-ok;} instruction in question
225 * registers defined by an instruction with no side effect.
|
| /external/compiler-rt/lib/builtins/ |
| clear_cache.c | 32 * clear_mips_cache - Invalidates instruction cache for Mips.
63 instruction after the last nop.
65 "jr.hb $ra\n" /* Return, clearing instruction
83 * It is expected to invalidate the instruction cache for the
90 * Intel processors have a unified instruction and data cache
|
| /external/lldb/source/Expression/ |
| IRDynamicChecks.cpp | 190 /// Add instrumentation to a single instruction
193 /// The instruction to be instrumented.
198 virtual bool InstrumentInstruction(llvm::Instruction *inst) = 0;
201 /// Register a single instruction to be instrumented
204 /// The instruction to be instrumented.
206 void RegisterInstruction(llvm::Instruction &i)
212 /// Determine whether a single instruction is interesting to
216 /// The instruction to be inspected.
221 virtual bool InspectInstruction(llvm::Instruction &i)
333 typedef std::vector <llvm::Instruction *> InstVector
[all...] |
| /external/llvm/docs/CommandGuide/ |
| tblgen.rst | 78 Generate instruction descriptions.
90 Generate pseudo instruction lowering.
94 Generate a DAG (Directed Acycle Graph) instruction selector.
98 Generate assembly instruction matcher.
106 Generate a "fast" instruction selector.
|
