| /external/llvm/test/MC/Mips/ |
| sym-expr.s | 11 jal __start + 0x4 # CHECK: instruction: [jal, Imm<__start+4>]
12 jal __start + (-0x10) # CHECK: instruction: [jal, Imm<__start-16>]
13 jal (__start + (-0x10)) # CHECK: instruction: [jal, Imm<__start-16>]
|
| /external/llvm/test/TableGen/ |
| DefmInsideMultiClass.td | 7 class Instruction<bits<4> opc, string Name> {
13 def rr : Instruction<opc, "rr">;
14 def rm : Instruction<opc, "rm">;
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/iface/instruction/ |
| Instruction.java | 32 package org.jf.dexlib2.iface.instruction;
37 * This class represents a generic instruction.
39 * There are two categories of sub-interfaces of this interface. The dexlib2.iface.instruction.* interfaces are set of
40 * generic categories of instructions, while the dexlib2.iface.instruction.formats.* interfaces each represent a
41 * specific instruction format, and are typically built up as a composite of generic instruction interfaces.
43 public interface Instruction {
45 * Gets the opcode of this instruction.
47 * @return The Opcode of this instruction.
52 * Gets the size of this instruction
[all...] |
| /art/compiler/optimizing/ |
| find_loops_test.cc | 43 Instruction::CONST_4 | 0 | 0,
44 Instruction::RETURN_VOID);
56 Instruction::CONST_4 | 0 | 0,
57 Instruction::RETURN);
69 Instruction::CONST_4 | 3 << 12 | 0,
70 Instruction::CONST_4 | 4 << 12 | 1 << 8,
71 Instruction::ADD_INT_2ADDR | 1 << 12,
72 Instruction::GOTO | 0x100,
73 Instruction::RETURN);
85 Instruction::CONST_4 | 0 | 0
[all...] |
| liveness_test.cc | 95 Instruction::CONST_4 | 0 | 0,
96 Instruction::RETURN_VOID);
117 Instruction::CONST_4 | 0 | 0,
118 Instruction::RETURN);
143 Instruction::CONST_4 | 3 << 12 | 0,
144 Instruction::CONST_4 | 4 << 12 | 1 << 8,
145 Instruction::ADD_INT_2ADDR | 1 << 12,
146 Instruction::GOTO | 0x100,
147 Instruction::RETURN);
190 Instruction::CONST_4 | 0 | 0
[all...] |
| codegen_test.cc | 272 const uint16_t data[] = ZERO_REGISTER_CODE_ITEM(Instruction::RETURN_VOID);
278 Instruction::GOTO | 0x100,
279 Instruction::RETURN_VOID);
286 Instruction::GOTO | 0x100,
287 Instruction::GOTO | 0x100,
288 Instruction::RETURN_VOID);
295 Instruction::GOTO | 0x200,
296 Instruction::RETURN_VOID,
297 Instruction::GOTO | 0xFF00);
302 Instruction::GOTO_16, 3
[all...] |
| licm.cc | 22 static bool IsPhiOf(HInstruction* instruction, HBasicBlock* block) {
23 return instruction->IsPhi() && instruction->GetBlock() == block;
27 * Returns whether `instruction` has all its inputs and environment defined
30 static bool InputsAreDefinedBeforeLoop(HInstruction* instruction) {
31 DCHECK(instruction->IsInLoop());
32 HLoopInformation* info = instruction->GetBlock()->GetLoopInformation();
33 for (HInputIterator it(instruction); !it.Done(); it.Advance()) {
42 for (HEnvironment* environment = instruction->GetEnvironment();
50 // We can move an instruction that takes a loop header phi in the environment
115 HInstruction* instruction = inst_it.Current(); local
[all...] |
| /external/llvm/test/Analysis/CostModel/X86/ |
| alternate-shuffle-cost.ll | 19 ; SSE2: Cost Model: {{.*}} 1 for instruction: %1 = shufflevector
20 ; SSSE3: Cost Model: {{.*}} 1 for instruction: %1 = shufflevector
21 ; SSE41: Cost Model: {{.*}} 1 for instruction: %1 = shufflevector
22 ; AVX: Cost Model: {{.*}} 1 for instruction: %1 = shufflevector
23 ; AVX2: Cost Model: {{.*}} 1 for instruction: %1 = shufflevector
30 ; SSE2: Cost Model: {{.*}} 2 for instruction: %1 = shufflevector
31 ; SSSE3: Cost Model: {{.*}} 2 for instruction: %1 = shufflevector
32 ; SSE41: Cost Model: {{.*}} 1 for instruction: %1 = shufflevector
33 ; AVX: Cost Model: {{.*}} 1 for instruction: %1 = shufflevector
34 ; AVX2: Cost Model: {{.*}} 1 for instruction: %1 = shufflevecto
[all...] |
| /external/llvm/include/llvm/Transforms/InstCombine/ |
| InstCombineWorklist.h | 15 #include "llvm/IR/Instruction.h"
27 SmallVector<Instruction*, 256> Worklist;
28 DenseMap<Instruction*, unsigned> WorklistMap;
46 /// Add - Add the specified instruction to the worklist if it isn't already
48 void Add(Instruction *I) {
56 if (Instruction *I = dyn_cast<Instruction>(V))
63 void AddInitialGroup(Instruction *const *List, unsigned NumEntries) {
69 Instruction *I = List[NumEntries-1];
76 void Remove(Instruction *I)
[all...] |
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64.s | 8 clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 jr.hb $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 jalr.hb $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 jalr.hb $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/proguard/src/proguard/optimize/peephole/ |
| InstructionSequencesReplacer.java | 25 import proguard.classfile.instruction.Instruction;
26 import proguard.classfile.instruction.visitor.*;
29 * This InstructionVisitor replaces multiple instruction sequences at once.
45 * instruction.
46 * @param instructionSequences the instruction sequences to be replaced,
49 * and the instruction index in the sequence.
57 Instruction[][][] instructionSequences,
72 * instruction.
73 * @param instructionSequences the instruction sequences to be replaced
[all...] |
| /external/llvm/lib/IR/ |
| Instruction.cpp | 1 //===-- Instruction.cpp - Implement the Instruction class -----------------===//
10 // This file implements the Instruction class for the IR library.
14 #include "llvm/IR/Instruction.h"
23 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps,
24 Instruction *InsertBefore)
27 // If requested, insert this instruction into a basic block...
30 "Instruction to insert before is not in a basic block!");
35 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps
[all...] |
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64r2.s | 8 clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips32r2.s | 8 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64.s | 9 clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
18 maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/mockito/cglib-and-asm/src/org/mockito/asm/tree/ |
| AbstractInsnNode.java | 38 * A node that represents a bytecode instruction. <i>An instruction can appear
121 * The opcode of this instruction.
126 * Previous instruction in the list to which this instruction belongs.
131 * Next instruction in the list to which this instruction belongs.
136 * Index of this instruction in the list to which it belongs. The value of
138 * value of -1 indicates that this instruction does not belong to any
146 * @param opcode the opcode of the instruction to be constructed.
[all...] |
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips5.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips4.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /art/tools/dexfuzz/src/dexfuzz/rawdex/formats/ |
| ContainsTarget.java | 19 import dexfuzz.rawdex.Instruction;
22 * Every Format that contains an offset to a target instruction
26 public long getTarget(Instruction insn);
28 public void setTarget(Instruction insn, long target);
|
| /dalvik/dx/tests/031-bb-dead-code/ |
| blort.j | 26 ; dead code after the last reachable instruction in a method
32 ; dead code after the last reachable instruction in a method
39 ; dead code after the last reachable instruction in a method
60 ; dead code after goto instruction
68 ; dead code after ret instruction
77 ; dead code after tableswitch instruction
93 ; dead code after lookupswitch instruction
104 ; dead code after ireturn instruction
113 ; dead code after lreturn instruction
122 ; dead code after freturn instruction
[all...] |
| /external/llvm/test/Assembler/ |
| invalid-name.ll | 5 ; CHECK: expected instruction opcode
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips32r2.s | 8 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips32r2.s | 8 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
17 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips5-wrong-error.s | 8 bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
9 bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
