| /external/proguard/src/proguard/classfile/attribute/visitor/ |
| StackSizeComputer.java | 25 import proguard.classfile.instruction.*;
26 import proguard.classfile.instruction.visitor.InstructionVisitor;
33 * This AttributeVisitor computes the stack sizes at all instruction offsets
61 * Returns whether the instruction at the given offset is reachable in the
71 * Returns the stack size at the given instruction offset of the most
78 throw new IllegalArgumentException("Unknown stack size at unreachable instruction offset ["+instructionOffset+"]");
152 // Evaluate the instruction block starting at the entry point of the method.
166 // Some simple instructions exit from the current instruction block.
179 // Constant pool instructions never end the current instruction block.
187 // The ret instruction end the current instruction block
314 Instruction instruction = InstructionFactory.create(codeAttribute.code, local
[all...] |
| /external/llvm/include/llvm/IR/ |
| InstrTypes.h | 1 //===-- llvm/InstrTypes.h - Important Instruction subclasses ----*- C++ -*-===//
21 #include "llvm/IR/Instruction.h"
35 class TerminatorInst : public Instruction {
37 TerminatorInst(Type *Ty, Instruction::TermOps iType,
39 Instruction *InsertBefore = nullptr)
40 : Instruction(Ty, iType, Ops, NumOps, InsertBefore) {}
42 TerminatorInst(Type *Ty, Instruction::TermOps iType,
44 : Instruction(Ty, iType, Ops, NumOps, InsertAtEnd) {}
72 static inline bool classof(const Instruction *I) {
76 return isa<Instruction>(V) && classof(cast<Instruction>(V))
[all...] |
| Instruction.h | 1 //===-- llvm/Instruction.h - Instruction class definition -------*- C++ -*-===//
10 // This file contains the declaration of the Instruction class, which is the
33 struct ilist_traits<Instruction>
34 : public SymbolTableListTraits<Instruction, BasicBlock> {
40 Instruction *createSentinel() const;
41 static void destroySentinel(Instruction *) {}
43 Instruction *provideInitialHead() const { return createSentinel(); }
44 Instruction *ensureHead(Instruction *) const { return createSentinel();
[all...] |
| NoFolder.h | 40 Instruction *CreateAdd(Constant *LHS, Constant *RHS,
47 Instruction *CreateNSWAdd(Constant *LHS, Constant *RHS) const {
50 Instruction *CreateNUWAdd(Constant *LHS, Constant *RHS) const {
53 Instruction *CreateFAdd(Constant *LHS, Constant *RHS) const {
56 Instruction *CreateSub(Constant *LHS, Constant *RHS,
63 Instruction *CreateNSWSub(Constant *LHS, Constant *RHS) const {
66 Instruction *CreateNUWSub(Constant *LHS, Constant *RHS) const {
69 Instruction *CreateFSub(Constant *LHS, Constant *RHS) const {
72 Instruction *CreateMul(Constant *LHS, Constant *RHS,
79 Instruction *CreateNSWMul(Constant *LHS, Constant *RHS) const
[all...] |
| InstVisitor.h | 1 //===- InstVisitor.h - Instruction visitor templates ------------*- C++ -*-===//
24 // We operate on opaque instruction classes, so forward declare all instruction
28 #include "llvm/IR/Instruction.def"
35 /// @brief Base class for instruction visitors
37 /// Instruction visitors are used when you want to perform different actions
64 /// The defined has 'visit' methods for Instruction, and also for BasicBlock,
67 /// Note that if you don't implement visitXXX for some instruction type,
68 /// the visitXXX method for instruction superclass will be invoked. So
72 /// The optional second template argument specifies the type that instruction
[all...] |
| /external/llvm/test/MC/ARM/ |
| neon-crypto.s | 12 @ CHECK-V7: instruction requires: crypto armv8
13 @ CHECK-V7: instruction requires: crypto armv8
14 @ CHECK-V7: instruction requires: crypto armv8
15 @ CHECK-V7: instruction requires: crypto armv8
23 @ CHECK-V7: instruction requires: crypto armv8
24 @ CHECK-V7: instruction requires: crypto armv8
25 @ CHECK-V7: instruction requires: crypto armv8
41 @ CHECK-V7: instruction requires: crypto armv8
42 @ CHECK-V7: instruction requires: crypto armv8
43 @ CHECK-V7: instruction requires: crypto armv
[all...] |
| load-store-acquire-release-v8-thumb.s | 12 @ CHECK-V7: error: instruction requires: armv8
13 @ CHECK-V7: error: instruction requires: armv8
14 @ CHECK-V7: error: instruction requires: armv8
15 @ CHECK-V7: error: instruction requires: armv8
25 @ CHECK-V7: error: instruction requires: armv8
26 @ CHECK-V7: error: instruction requires: armv8
27 @ CHECK-V7: error: instruction requires: armv8
28 @ CHECK-V7: error: instruction requires: armv8
36 @ CHECK-V7: error: instruction requires: armv8
37 @ CHECK-V7: error: instruction requires: armv
[all...] |
| load-store-acquire-release-v8.s | 12 @ CHECK-V7: instruction requires: armv8
13 @ CHECK-V7: instruction requires: armv8
14 @ CHECK-V7: instruction requires: armv8
15 @ CHECK-V7: instruction requires: armv8
25 @ CHECK-V7: instruction requires: armv8
26 @ CHECK-V7: instruction requires: armv8
27 @ CHECK-V7: instruction requires: armv8
28 @ CHECK-V7: instruction requires: armv8
36 @ CHECK-V7: instruction requires: armv8
37 @ CHECK-V7: instruction requires: armv
[all...] |
| /external/llvm/test/MC/SystemZ/ |
| regs-bad.s | 6 #CHECK: error: invalid operand for instruction
8 #CHECK: error: invalid operand for instruction
10 #CHECK: error: invalid operand for instruction
12 #CHECK: error: invalid operand for instruction
14 #CHECK: error: invalid operand for instruction
16 #CHECK: error: invalid operand for instruction
28 #CHECK: error: invalid operand for instruction
30 #CHECK: error: invalid operand for instruction
32 #CHECK: error: invalid operand for instruction
34 #CHECK: error: invalid operand for instruction
[all...] |
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips4.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
14 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
16 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[all...] |
| /external/clang/test/CodeGenObjC/ |
| mrr-captured-block-var-inlined-layout.m | 23 // CHECK: Inline instruction for block variable layout: 0x0100
24 // CHECK-i386: Inline instruction for block variable layout: 0x0100
30 // CHECK: Inline instruction for block variable layout: 0x0210
31 // CHECK-i386: Inline instruction for block variable layout: 0x0210
39 // CHECK: Inline instruction for block variable layout: 0x0230
40 // CHECK-i386: Inline instruction for block variable layout: 0x0230
50 // CHECK: Inline instruction for block variable layout: 0x0230
51 // CHECK-i386: Inline instruction for block variable layout: 0x0230
61 // CHECK: Inline instruction for block variable layout: 0x020
62 // CHECK-i386: Inline instruction for block variable layout: 0x02
[all...] |
| /external/llvm/test/Analysis/CostModel/X86/ |
| vshift-cost.ll | 17 ; CHECK: Found an estimated cost of 1 for instruction: %shl
25 ; CHECK: Found an estimated cost of 1 for instruction: %shl
28 ; With SSE4.1, v4i32 shifts can be lowered into a single pmulld instruction.
38 ; SSE2: Found an estimated cost of 6 for instruction: %shl
39 ; SSE41: Found an estimated cost of 1 for instruction: %shl
40 ; AVX: Found an estimated cost of 1 for instruction: %shl
41 ; AVX2: Found an estimated cost of 1 for instruction: %shl
49 ; SSE2: Found an estimated cost of 6 for instruction: %shl
50 ; SSE41: Found an estimated cost of 1 for instruction: %shl
51 ; AVX: Found an estimated cost of 1 for instruction: %sh
[all...] |
| /external/llvm/unittests/Transforms/Utils/ |
| IntegerDivision.cpp | 42 EXPECT_TRUE(BB->front().getOpcode() == Instruction::SDiv);
47 EXPECT_TRUE(BB->front().getOpcode() == Instruction::AShr);
49 Instruction* Quotient = dyn_cast<Instruction>(cast<User>(Ret)->getOperand(0));
50 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::Sub);
72 EXPECT_TRUE(BB->front().getOpcode() == Instruction::UDiv);
77 EXPECT_TRUE(BB->front().getOpcode() == Instruction::ICmp);
79 Instruction* Quotient = dyn_cast<Instruction>(cast<User>(Ret)->getOperand(0));
80 EXPECT_TRUE(Quotient && Quotient->getOpcode() == Instruction::PHI)
[all...] |
| /external/v8/src/compiler/ |
| instruction-codes.h | 9 #include "src/compiler/arm/instruction-codes-arm.h"
11 #include "src/compiler/arm64/instruction-codes-arm64.h"
13 #include "src/compiler/ia32/instruction-codes-ia32.h"
15 #include "src/compiler/x64/instruction-codes-x64.h"
30 // Most opcodes specify a single instruction.
51 // Addressing modes represent the "shape" of inputs to an instruction.
53 // are encoded into the InstructionCode of the instruction and tell the
100 // what code to emit for an instruction in the code generator. It is not
106 // for code generation. We encode the instruction, addressing mode, and flags
108 // the instruction
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 10 // This file defines the target independent instruction opcodes.
19 /// Invariant opcodes: All instruction sets have these as their low opcodes.
21 /// Every instruction defined here must also appear in Target.td and the order
32 /// KILL - This instruction is a noop that is used only to adjust the
37 /// EXTRACT_SUBREG - This instruction takes two operands: a register
43 /// INSERT_SUBREG - This instruction takes three operands: a register that
54 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
56 /// often zero, because it is commonly used to assert that the instruction
60 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
62 /// used between instruction selection and MachineInstr creation, befor
[all...] |
| /art/compiler/dex/ |
| gvn_dead_code_elimination.cc | 509 mir->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpNop);
517 mir->dalvikInsn.opcode = static_cast<Instruction::Code>(
518 mir->dalvikInsn.opcode - Instruction::ADD_INT_2ADDR + Instruction::ADD_INT);
524 phi->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpPhi);
[all...] |
| /external/proguard/src/proguard/classfile/instruction/ |
| BranchInstruction.java | 21 package proguard.classfile.instruction;
25 import proguard.classfile.instruction.visitor.InstructionVisitor;
28 * This interface describes an instruction that branches to a given offset in
33 public class BranchInstruction extends Instruction
52 * Copies the given instruction into this instruction.
53 * @param branchInstruction the instruction to be copied.
54 * @return this instruction.
65 // Implementations for Instruction.
80 public Instruction shrink(
[all...] |
| /external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/Format/ |
| InstructionMethodItem.java | 40 import org.jf.dexlib2.iface.instruction.*;
41 import org.jf.dexlib2.iface.instruction.formats.Instruction20bc;
42 import org.jf.dexlib2.iface.instruction.formats.Instruction31t;
43 import org.jf.dexlib2.iface.instruction.formats.UnknownInstruction;
56 public class InstructionMethodItem<T extends Instruction> extends MethodItem {
58 @Nonnull protected final T instruction; field in class:InstructionMethodItem
60 public InstructionMethodItem(@Nonnull MethodDefinition methodDef, int codeAddress, @Nonnull T instruction) {
63 this.instruction = instruction;
87 Opcode opcode = instruction.getOpcode()
384 FiveRegisterInstruction instruction = (FiveRegisterInstruction)this.instruction; local
429 RegisterRangeInstruction instruction = (RegisterRangeInstruction)this.instruction; local
[all...] |
| /art/runtime/ |
| dex_instruction_visitor.h | 33 const Instruction* inst = Instruction::At(&code[i]);
36 case Instruction::cname: { \
52 // Specific handlers for each instruction.
54 void Do_ ## cname(const Instruction* inst) { \
63 // The default instruction handler.
64 void Do_Default(const Instruction*) {
|
| common_throws.cc | 367 const Instruction* instr = Instruction::At(&code->insns_[throw_dex_pc]);
369 case Instruction::INVOKE_DIRECT:
372 case Instruction::INVOKE_DIRECT_RANGE:
375 case Instruction::INVOKE_VIRTUAL:
378 case Instruction::INVOKE_VIRTUAL_RANGE:
381 case Instruction::INVOKE_INTERFACE:
384 case Instruction::INVOKE_INTERFACE_RANGE:
387 case Instruction::INVOKE_VIRTUAL_QUICK:
388 case Instruction::INVOKE_VIRTUAL_RANGE_QUICK:
[all...] |
| /art/tools/dexfuzz/src/dexfuzz/rawdex/formats/ |
| AbstractFormat.java | 20 import dexfuzz.rawdex.Instruction;
26 * methods to write out a provided Instruction according to this format, and also methods
27 * to read the vregs from an Instruction's raw bytes.
43 * Get the size of an Instruction that has this format.
48 * Given a file handle and an instruction, write that Instruction out to the file
51 public abstract void writeToFile(DexRandomAccessFile file, Instruction insn) throws IOException;
|
| /external/lzma/C/ |
| BraIA64.c | 29 UInt64 instruction, instNorm;
local
35 instruction = 0;
37 instruction += (UInt64)data[i + j + bytePos] << (8 * j);
39 instNorm = instruction >> bitRes;
59 instruction &= (1 << bitRes) - 1;
60 instruction |= (instNorm << bitRes);
62 data[i + j + bytePos] = (Byte)(instruction >> (8 * j));
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_target_nv50.h | 47 virtual bool insnCanLoad(const Instruction *insn, int s,
48 const Instruction *ld) const;
51 virtual bool isModSupported(const Instruction *, int s, Modifier) const;
52 virtual bool isSatSupported(const Instruction *) const;
53 virtual bool mayPredicate(const Instruction *, const Value *) const;
55 virtual int getLatency(const Instruction *) const;
56 virtual int getThroughput(const Instruction *) const;
|
| /art/compiler/optimizing/ |
| graph_visualizer.cc | 161 void VisitParallelMove(HParallelMove* instruction) OVERRIDE {
163 for (size_t i = 0, e = instruction->NumMoves(); i < e; ++i) {
164 MoveOperands* move = instruction->MoveOperandsAt(i);
173 output_ << " (liveness: " << instruction->GetLifetimePosition() << ")";
176 void VisitIntConstant(HIntConstant* instruction) OVERRIDE {
177 output_ << " " << instruction->GetValue();
180 void VisitLongConstant(HLongConstant* instruction) OVERRIDE {
181 output_ << " " << instruction->GetValue();
184 void VisitFloatConstant(HFloatConstant* instruction) OVERRIDE {
185 output_ << " " << instruction->GetValue()
272 HInstruction* instruction = it.Current(); local
321 HInstruction* instruction = it.Current(); variable
[all...] |
| /external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/ |
| PreInstructionRegisterInfoMethodItem.java | 35 import org.jf.dexlib2.iface.instruction.*;
109 RegisterRangeInstruction instruction = (RegisterRangeInstruction)analyzedInstruction.getInstruction(); local
111 registers.set(instruction.getStartRegister(),
112 instruction.getStartRegister() + instruction.getRegisterCount());
114 FiveRegisterInstruction instruction = (FiveRegisterInstruction)analyzedInstruction.getInstruction(); local
115 int regCount = instruction.getRegisterCount();
118 registers.set(instruction.getRegisterG());
121 registers.set(instruction.getRegisterF());
124 registers.set(instruction.getRegisterE())
133 ThreeRegisterInstruction instruction = (ThreeRegisterInstruction)analyzedInstruction.getInstruction(); local
138 TwoRegisterInstruction instruction = (TwoRegisterInstruction)analyzedInstruction.getInstruction(); local
142 OneRegisterInstruction instruction = (OneRegisterInstruction)analyzedInstruction.getInstruction(); local
[all...] |
