| /external/llvm/test/MC/Disassembler/SystemZ/ |
| unmapped.txt | 3 # An unmapped 2-byte instruction
5 # CHECK: warning: invalid instruction encoding
11 # An unmapped 4-byte instruction
13 # CHECK-NEXT: warning: invalid instruction encoding
19 # An unmapped 6-byte instruction
21 # CHECK-NEXT: warning: invalid instruction encoding
29 # CHECK-NEXT: warning: invalid instruction encoding
|
| /art/compiler/optimizing/ |
| locations.cc | 23 LocationSummary::LocationSummary(HInstruction* instruction,
26 : inputs_(instruction->GetBlock()->GetGraph()->GetArena(), instruction->InputCount()),
27 temps_(instruction->GetBlock()->GetGraph()->GetArena(), 0),
34 inputs_.SetSize(instruction->InputCount());
35 for (size_t i = 0; i < instruction->InputCount(); ++i) {
38 instruction->SetLocations(this);
41 ArenaAllocator* arena = instruction->GetBlock()->GetGraph()->GetArena();
47 Location Location::RegisterOrConstant(HInstruction* instruction) {
48 return instruction->IsConstant(
[all...] |
| instruction_simplifier.cc | 49 void VisitTypeConversion(HTypeConversion* instruction) OVERRIDE;
50 void VisitNullCheck(HNullCheck* instruction) OVERRIDE;
51 void VisitArrayLength(HArrayLength* instruction) OVERRIDE;
52 void VisitCheckCast(HCheckCast* instruction) OVERRIDE;
53 void VisitAdd(HAdd* instruction) OVERRIDE;
54 void VisitAnd(HAnd* instruction) OVERRIDE;
55 void VisitDiv(HDiv* instruction) OVERRIDE;
56 void VisitMul(HMul* instruction) OVERRIDE;
57 void VisitNeg(HNeg* instruction) OVERRIDE;
58 void VisitNot(HNot* instruction) OVERRIDE
[all...] |
| linearize_test.cc | 77 Instruction::CONST_4 | 0 | 0,
78 Instruction::IF_EQ, 5,
79 Instruction::IF_EQ, 0xFFFE,
80 Instruction::GOTO | 0xFE00,
81 Instruction::RETURN_VOID);
102 Instruction::CONST_4 | 0 | 0,
103 Instruction::IF_EQ, 3,
104 Instruction::RETURN_VOID,
105 Instruction::IF_EQ, 0xFFFD,
106 Instruction::GOTO | 0xFE00)
[all...] |
| suspend_check_test.cc | 41 // Account for some tests having a store local as first instruction.
48 Instruction::NOP,
49 Instruction::GOTO | 0xFF00);
56 Instruction::GOTO_32, 0, 0);
63 Instruction::CONST_4 | 0 | 0,
64 Instruction::IF_EQ, 0xFFFF,
65 Instruction::RETURN_VOID);
72 Instruction::CONST_4 | 0 | 0,
73 Instruction::IF_NE, 0xFFFF,
74 Instruction::RETURN_VOID)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineInternal.h | 63 if (isa<Instruction>(V)) {
105 if (BO->getOpcode() == Instruction::Add ||
106 BO->getOpcode() == Instruction::Sub)
159 void InsertHelper(Instruction *I, const Twine &Name, BasicBlock *BB,
170 /// \brief The core instruction combiner logic.
176 : public InstVisitor<InstCombiner, Instruction *> {
226 // Visitation implementation - Implement instruction combining for different
227 // instruction types. The semantics are as follows:
231 // otherwise - Change was made, replace I with returned instruction
233 Instruction *visitAdd(BinaryOperator &I)
[all...] |
| /art/compiler/dex/ |
| dex_to_dex_compiler.cc | 61 void CompileReturnVoid(Instruction* inst, uint32_t dex_pc);
64 // this case, returns the second NOP instruction pointer. Otherwise, returns
66 Instruction* CompileCheckCast(Instruction* inst, uint32_t dex_pc);
74 void CompileInstanceFieldAccess(Instruction* inst, uint32_t dex_pc,
75 Instruction::Code new_opcode, bool is_put);
83 void CompileInvokeVirtual(Instruction* inst, uint32_t dex_pc,
84 Instruction::Code new_opcode, bool is_range);
98 Instruction* inst = const_cast<Instruction*>(Instruction::At(insns))
[all...] |
| /external/llvm/test/MC/ARM/ |
| directive-arch_extension-crc.s | 18 @ CHECK-V7: error: instruction requires: crc armv8
20 @ CHECK-V7: error: instruction requires: crc armv8
22 @ CHECK-V7: error: instruction requires: crc armv8
25 @ CHECK-V7: error: instruction requires: crc armv8
27 @ CHECK-V7: error: instruction requires: crc armv8
29 @ CHECK-V7: error: instruction requires: crc armv8
39 @ CHECK-V7: error: instruction requires: crc armv8
40 @ CHECK-V8: error: instruction requires: crc
42 @ CHECK-V7: error: instruction requires: crc armv8
43 @ CHECK-V8: error: instruction requires: cr
[all...] |
| thumb2-dsp-diag.s | 9 ; CHECK-ERRORS: error: instruction requires: arm-mode
10 ; CHECK-ERRORS: error: instruction requires: arm-mode
11 ; CHECK-ERRORS: error: instruction requires: arm-mode
12 ; CHECK-ERRORS: error: instruction requires: arm-mode
13 ; CHECK-ERRORS: error: invalid operand for instruction
20 ; CHECK-ERRORS: error: instruction requires: arm-mode
21 ; CHECK-ERRORS: error: instruction requires: arm-mode
22 ; CHECK-ERRORS: error: instruction requires: arm-mode
23 ; CHECK-ERRORS: error: instruction requires: arm-mode
24 ; CHECK-ERRORS: error: invalid operand for instruction
[all...] |
| directive-arch_extension-simd.s | 20 @ CHECK-V7: error: instruction requires: FPARMv8
22 @ CHECK-V7: error: instruction requires: FPARMv8
25 @ CHECK-V7: error: instruction requires: FPARMv8
27 @ CHECK-V7: error: instruction requires: FPARMv8
30 @ CHECK-V7: error: instruction requires: FPARMv8
32 @ CHECK-V7: error: instruction requires: FPARMv8
34 @ CHECK-V7: error: instruction requires: FPARMv8
36 @ CHECK-V7: error: instruction requires: FPARMv8
38 @ CHECK-V7: error: instruction requires: FPARMv8
40 @ CHECK-V7: error: instruction requires: FPARMv
[all...] |
| invalid-crc32.s | 11 @ CHECK: error: instruction 'crc32cb' is not predicable, but condition code specified
12 @ CHECK: error: instruction 'crc32b' is not predicable, but condition code specified
13 @ CHECK: error: instruction 'crc32ch' is not predicable, but condition code specified
14 @ CHECK: error: instruction 'crc32h' is not predicable, but condition code specified
15 @ CHECK: error: instruction 'crc32cw' is not predicable, but condition code specified
16 @ CHECK: error: instruction 'crc32w' is not predicable, but condition code specified
|
| thumb2-exception-return-mclass.s | 5 # CHECK: instruction requires: !armv*m
9 # CHECK: instruction requires: !armv*m
13 # CHECK: instruction requires: !armv*m
|
| thumb2-strd.s | 5 @ CHECK: error: invalid operand for instruction
6 @ CHECK: error: invalid operand for instruction
7 @ CHECK: error: invalid operand for instruction
|
| /external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/Format/ |
| InstructionMethodItemFactory.java | 33 import org.jf.dexlib2.iface.instruction.Instruction;
34 import org.jf.dexlib2.iface.instruction.OffsetInstruction;
35 import org.jf.dexlib2.iface.instruction.formats.ArrayPayload;
36 import org.jf.dexlib2.iface.instruction.formats.PackedSwitchPayload;
37 import org.jf.dexlib2.iface.instruction.formats.SparseSwitchPayload;
44 MethodDefinition methodDef, int codeAddress, Instruction instruction) {
46 if (instruction instanceof OffsetInstruction) {
48 (OffsetInstruction)instruction);
[all...] |
| /external/llvm/test/MC/X86/ |
| intel-syntax-ambiguous.s | 8 // CHECK: error: ambiguous operand size for instruction 'inc'
18 // CHECK: error: ambiguous operand size for instruction 'dec'
20 // CHECK: error: ambiguous operand size for instruction 'mov'
22 // CHECK: error: ambiguous operand size for instruction 'and'
24 // CHECK: error: ambiguous operand size for instruction 'or'
26 // CHECK: error: ambiguous operand size for instruction 'add'
28 // CHECK: error: ambiguous operand size for instruction 'sub'
38 // CHECK: error: invalid operand for instruction
41 // CHECK: error: invalid operand for instruction
47 // CHECK: error: ambiguous operand size for instruction 'fadd
[all...] |
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/ |
| AnalyzedInstruction.java | 34 import org.jf.dexlib2.iface.instruction.*;
44 * The actual instruction
46 protected Instruction instruction; field in class:AnalyzedInstruction
49 * The index of the instruction, where the first instruction in the method is at index 0, and so on
64 * This contains the register types *before* the instruction has executed
69 * This contains the register types *after* the instruction has executed
74 * When deodexing, we might need to deodex this instruction multiple times, when we merge in new register
75 * information. When this happens, we need to restore the original (odexed) instruction, so we can deodex it agai
[all...] |
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips4-wrong-error.s | 9 bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
13 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
14 ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15 ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
16 ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
17 lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
18 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[all...] |
| invalid-mips5-wrong-error.s | 9 abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
[all...] |
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips5-wrong-error.s | 9 abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
[all...] |
| invalid-mips32.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 jr.hb $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 jalr.hb $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 jalr.hb $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips5-wrong-error.s | 9 abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
[all...] |
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips5-wrong-error.s | 9 abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
[all...] |
| /art/test/471-deopt-environment/ |
| info.txt | 2 uses to generate a HDeoptimization instruction with an
|
| /art/test/479-regression-implicit-null-check/ |
| info.txt | 1 Tests a regression in which we moved the null check to an instruction which
|
| /art/test/481-regression-phi-cond/ |
| info.txt | 2 to remove a Phi from the wrong instruction list.
|
