| /external/llvm/lib/Target/Hexagon/ |
| HexagonFixupHwLoops.cpp | 8 // The loop start address in the LOOPn instruction is encoded as a distance
9 // from the LOOPn instruction itself. If the start address is too far from
10 // the LOOPn instruction, the loop needs to be set up manually, i.e. via
59 /// \brief Check the offset between each loop instruction and
60 /// the loop basic block to determine if we can use the LOOP instruction
64 /// \brief Add the instruction to set the LC and SA registers explicitly.
82 /// \brief Returns true if the instruction is a hardware loop instruction.
96 /// loop instruction then we need to set the LC0 and SA0 registers
105 // Offset of the current instruction from the start
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsOs16.cpp | 82 const Instruction &Inst = *I;
84 case Instruction::FAdd:
85 case Instruction::FSub:
86 case Instruction::FMul:
87 case Instruction::FDiv:
88 case Instruction::FRem:
89 case Instruction::FPToUI:
90 case Instruction::FPToSI:
91 case Instruction::UIToFP:
92 case Instruction::SIToFP
[all...] |
| /external/mockito/cglib-and-asm/src/org/mockito/asm/tree/ |
| InsnList.java | 58 * The first instruction in this list. May be <tt>null</tt>.
63 * The last instruction in this list. May be <tt>null</tt>.
83 * Returns the first instruction in this list.
85 * @return the first instruction in this list, or <tt>null</tt> if the
93 * Returns the last instruction in this list.
95 * @return the last instruction in this list, or <tt>null</tt> if the list
103 * Returns the instruction whose index is given. This method builds a cache
108 * @param index the index of the instruction that must be returned.
109 * @return the instruction whose index is given.
123 * Returns <tt>true</tt> if the given instruction belongs to this list.
[all...] |
| /external/proguard/src/proguard/optimize/peephole/ |
| BranchTargetFinder.java | 28 import proguard.classfile.instruction.*;
29 import proguard.classfile.instruction.visitor.InstructionVisitor;
35 * This AttributeVisitor finds all instruction offsets, branch targets, and
57 // (e.g. due to a break instruction in Java code), and we want to avoid
64 private static final short INSTRUCTION = 1 << 0;
93 * Returns whether there is an instruction at the given offset in the
98 return (instructionMarks[offset] & INSTRUCTION) != 0;
103 * Returns whether the instruction at the given offset is the target of
117 * Returns whether the instruction at the given offset is the origin of a
118 * branch instruction in the CodeAttribute that was visited most recently
[all...] |
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | 111 typedef SmallPtrSet<Instruction *, 16> SetOfInstrs;
117 typedef DenseMap<Instruction *, TypeIsSExt> InstrToOrigTy;
129 /// next instruction to optimize. Xforms that can invalidate this should
140 /// Keeps track of the type of the related instruction before their
172 bool OptimizeInst(Instruction *I, bool& ModifiedDT);
173 bool OptimizeMemoryInst(Instruction *I, Value *Addr, Type *AccessTy);
176 bool MoveExtToFormExtLoad(Instruction *&I);
177 bool OptimizeExtUses(Instruction *I);
180 bool OptimizeExtractElementInst(Instruction *Inst);
185 Instruction *&Inst
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| BypassSlowDivision.cpp | 74 // insertFastDiv - Substitutes the div/rem instruction with code that checks the
75 // value of the operands and uses a shorter-faster div/rem instruction when
76 // possible and the longer-slower div/rem instruction otherwise.
84 // Get instruction operands
85 Instruction *Instr = J;
122 Value *ShortDivisorV = FastBuilder.CreateCast(Instruction::Trunc, Divisor,
124 Value *ShortDividendV = FastBuilder.CreateCast(Instruction::Trunc, Dividend,
132 Value *FastQuotientV = FastBuilder.CreateCast(Instruction::ZExt,
135 Value *FastRemainderV = FastBuilder.CreateCast(Instruction::ZExt,
171 // point iterator J at first instruction of successorB
[all...] |
| /external/v8/src/mips64/ |
| disasm-mips64.cc | 5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be
60 // Writes one disassembled instruction into 'buffer' (0-terminated).
61 // Returns the length of the disassembled machine instruction in bytes.
62 int InstructionDecode(byte* instruction);
72 void PrintRs(Instruction* instr);
73 void PrintRt(Instruction* instr);
74 void PrintRd(Instruction* instr);
75 void PrintFs(Instruction* instr);
76 void PrintFt(Instruction* instr)
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| MemoryDependenceAnalysis.h | 28 class Instruction;
44 /// Clobber - This is a dependence on the specified instruction which
46 /// pair holds the instruction that clobbers the memory. For example,
56 /// Def - This is a dependence on the specified instruction which
58 /// the MemDepResult pair holds the instruction that defines the memory.
66 /// 2. For loads and stores, this could be an allocation instruction. In
77 /// upper part of the pair (i.e. the Instruction*)
81 /// (i.e. the Instruction* part) is instead used to encode more detailed
96 typedef PointerIntPair<Instruction*, 2, DepType> PairTy;
104 static MemDepResult getDef(Instruction *Inst)
[all...] |
| /external/llvm/lib/Transforms/ObjCARC/ |
| ARCInstKind.cpp | 80 llvm_unreachable("Unknown instruction class!");
227 if (const Instruction *I = dyn_cast<Instruction>(V)) {
228 // Any instruction other than bitcast and gep with a pointer operand have a
235 case Instruction::Call: {
252 case Instruction::Invoke:
255 case Instruction::BitCast:
256 case Instruction::GetElementPtr:
257 case Instruction::Select:
258 case Instruction::PHI
[all...] |
| /art/compiler/dex/ |
| mir_graph.cc | 167 * Parse an instruction, return the length of the instruction
170 const Instruction* inst = Instruction::At(code_ptr);
188 MIR* prev = nullptr; // Will be set to instruction before split.
197 // Now insn is at the instruction where we want to split, namely
198 // insn will be the first instruction of the "bottom" block.
199 // Similarly, prev will be the last instruction of the "top" block
306 // Does this containing block start with the desired instruction?
331 * first half of a potentially throwing instruction that has been split int
[all...] |
| /art/compiler/optimizing/ |
| graph_checker.h | 42 // Check `instruction`.
43 void VisitInstruction(HInstruction* instruction) OVERRIDE;
45 // Perform control-flow graph checks on instruction.
116 void VisitInstruction(HInstruction* instruction) OVERRIDE;
120 void VisitIf(HIf* instruction) OVERRIDE;
121 void VisitBooleanNot(HBooleanNot* instruction) OVERRIDE;
122 void VisitConstant(HConstant* instruction) OVERRIDE;
124 void HandleBooleanInput(HInstruction* instruction, size_t input_index);
|
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| OutputCollector.java | 31 * {@code non-null;} the associated finisher (which holds the instruction
57 * Adds an instruction to the output.
59 * @param insn {@code non-null;} the instruction to add
68 * indicated instruction really is a reversible branch.
71 * {@code 0} is the most recently added instruction,
72 * {@code 1} is the instruction before that, etc.
80 * Adds an instruction to the output suffix.
82 * @param insn {@code non-null;} the instruction to add
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| OutputCollector.java | 32 * {@code non-null;} the associated finisher (which holds the instruction
60 * Adds an instruction to the output.
62 * @param insn {@code non-null;} the instruction to add
71 * indicated instruction really is a reversible branch.
74 * {@code 0} is the most recently added instruction,
75 * {@code 1} is the instruction before that, etc.
83 * Adds an instruction to the output suffix.
85 * @param insn {@code non-null;} the instruction to add
|
| /external/clang/test/CodeGen/ |
| asm-errors.c | 10 // CRASH-REPORT: error: invalid instruction mnemonic 'abc'
14 // CHECK: error: invalid instruction mnemonic 'abc'
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| OutputCollector.java | 33 * {@code non-null;} the associated finisher (which holds the instruction
60 * Adds an instruction to the output.
62 * @param insn {@code non-null;} the instruction to add
71 * indicated instruction really is a reversible branch.
74 * {@code 0} is the most recently added instruction,
75 * {@code 1} is the instruction before that, etc.
83 * Adds an instruction to the output suffix.
85 * @param insn {@code non-null;} the instruction to add
|
| /external/kernel-headers/original/uapi/asm-arm/asm/ |
| byteorder.h | 7 * and word accesses (data or instruction) appear as:
12 * and word accesses (data or instruction) appear as:
|
| /external/libavc/encoder/x86/ |
| ih264e_platform_macros.h | 133 * memory accesses that appear in program order before the DMB instruction are
135 * after the DMB instruction. It does not affect the ordering of any other
139 * instruction in program order after this instruction executes until this instruction
140 * completes. This instruction completes when:
141 * 1. All explicit memory accesses before this instruction complete.
143 * this instruction complete.
|
| /external/llvm/lib/Transforms/Scalar/ |
| ADCE.cpp | 56 SmallPtrSet<Instruction*, 128> Alive;
57 SmallVector<Instruction*, 128> Worklist;
60 for (Instruction &I : inst_range(F)) {
70 Instruction *Curr = Worklist.pop_back_val();
72 if (Instruction *Inst = dyn_cast<Instruction>(OI))
82 for (Instruction &I : inst_range(F)) {
89 for (Instruction *&I : Worklist) {
|
| /external/llvm/test/Analysis/BasicAA/ |
| 2003-02-26-AccessSizeTest.ll | 2 ; is performed. It is not legal to delete the second load instruction because
3 ; the value computed by the first load instruction is changed by the store.
|
| /external/llvm/test/CodeGen/ARM/ |
| 2010-10-25-ifcvt-ldm.ll | 3 ; LDM instruction, was causing an assertion failure because the microop count
4 ; was being treated as an instruction count.
|
| /external/llvm/test/CodeGen/Mips/ |
| machineverifier.ll | 2 ; Make sure machine verifier understands the last instruction of a basic block
3 ; is not the terminator instruction after delay slot filler pass is run.
|
| /external/llvm/test/CodeGen/X86/ |
| 2005-01-17-CycleInDAG.ll | 2 ; load into the sub instruction here as it induces a cycle in the dag, which
3 ; is invalid code (there is no correct way to order the instruction). Check
|
| /external/llvm/test/MC/ARM/ |
| fp-const-errors.s | 5 @ CHECK: error: invalid operand for instruction
8 @ CHECK: error: invalid operand for instruction
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| armv8.1a.txt | 12 # CHECK-V8: warning: invalid instruction encoding
14 # CHECK-V8: warning: invalid instruction encoding
16 # CHECK-V8: warning: invalid instruction encoding
18 # CHECK-V8: warning: invalid instruction encoding
29 # CHECK-V8: warning: invalid instruction encoding
31 # CHECK-V8: warning: invalid instruction encoding
33 # CHECK-V8: warning: invalid instruction encoding
35 # CHECK-V8: warning: invalid instruction encoding
|
| /external/llvm/test/Transforms/LoopStrengthReduce/ |
| exit_compare_live_range.ll | 1 ; Make sure that the compare instruction occurs after the increment to avoid
3 ; instruction immediately before the conditional branch.
|
