| /dalvik/dx/tests/100-local-mismatch/ |
| info.txt | 2 variable table entry fundamentally disagrees with an instruction that
|
| /external/lldb/source/Plugins/ |
| CMakeLists.txt | 4 add_subdirectory(Instruction)
|
| /external/llvm/test/Assembler/ |
| invalid-name2.ll | 5 ; CHECK: expected instruction opcode
|
| /external/llvm/test/MC/ARM/ |
| thumb-invalid-crypto.txt | 5 @ CHECK: error: instruction 'aesd' is not predicable, but condition code specified
7 @ CHECK: error: instruction 'aesimc' is not predicable, but condition code specified
9 @ CHECK: error: instruction 'aesmc' is not predicable, but condition code specified
11 @ CHECK: error: instruction 'aese' is not predicable, but condition code specified
15 @ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified
17 @ CHECK: error: instruction 'sha1su1' is not predicable, but condition code specified
19 @ CHECK: error: instruction 'sha256su0' is not predicable, but condition code specified
23 @ CHECK: error: instruction 'sha1c' is not predicable, but condition code specified
25 @ CHECK: error: instruction 'sha1m' is not predicable, but condition code specified
27 @ CHECK: error: instruction 'sha1p' is not predicable, but condition code specifie
[all...] |
| v8_IT_manual.s | 11 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
14 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
18 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
30 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
34 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
42 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
46 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
50 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
59 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
71 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT bloc
[all...] |
| not-armv4.s | 4 @ CHECK: error: instruction requires: armv5t
7 @ CHECK: error: instruction requires: armv6t2
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips3-wrong-error.s | 8 ldl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 ldr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 sdl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11 sdr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 ldle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 ldre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 sdle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 sdre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
17 lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[all...] |
| invalid-mips1.s | 8 add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 c.sf.s $f14,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips3.s | 8 addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 mthi $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips64.s | 8 addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 daddi $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 dadd $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 dadd $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 dmult $s7,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/v8/src/arm64/ |
| decoder-arm64.h | 71 #define DECLARE(A) virtual void Visit##A(Instruction* instr) = 0;
85 // visitor classes when decoding reaches the leaf node of the instruction
112 #define DECLARE(A) void Visit##A(Instruction* instr);
128 // Top-level instruction decoder function. Decodes an instruction and calls
130 virtual void Decode(Instruction *instr);
133 // Decode the PC relative addressing instruction, and call the corresponding
135 // On entry, instruction bits 27:24 = 0x0.
136 void DecodePCRelAddressing(Instruction* instr);
138 // Decode the add/subtract immediate instruction, and call the correspondin
[all...] |
| /external/vixl/src/vixl/a64/ |
| disasm-a64.h | 46 #define DECLARE(A) virtual void Visit##A(const Instruction* instr);
51 virtual void ProcessOutput(const Instruction* instr);
59 virtual void AppendRegisterNameToOutput(const Instruction* instr,
64 virtual void AppendPCRelativeOffsetToOutput(const Instruction* instr,
68 // used for example to print the target address of an ADR instruction.
69 virtual void AppendCodeRelativeAddressToOutput(const Instruction* instr,
77 virtual void AppendCodeRelativeCodeAddressToOutput(const Instruction* instr,
82 // instruction.
83 virtual void AppendCodeRelativeDataAddressToOutput(const Instruction* instr,
88 virtual void AppendAddressToOutput(const Instruction* instr
[all...] |
| decoder-a64.h | 125 #define DECLARE(A) virtual void Visit##A(const Instruction* instr) = 0;
130 Instruction* MutableInstruction(const Instruction* instr) {
132 return const_cast<Instruction*>(instr);
145 void Decode(const Instruction* instr) {
152 void Decode(Instruction* instr) {
153 DecodeInstruction(const_cast<const Instruction*>(instr));
158 // visitor classes when decoding reaches the leaf node of the instruction
195 #define DECLARE(A) void Visit##A(const Instruction* instr);
203 // Decodes an instruction and calls the visitor functions registered with th
[all...] |
| /ndk/tests/build/issue21132-__ARM_ARCH__/jni/ |
| Application.mk | 1 # Only armeabi-v7a* and x86 instruction for fast __swap32md
|
| /art/compiler/dex/quick/ |
| mir_to_lir.cc | 252 case InlineMethodAnalyser::IGetVariant(Instruction::IGET):
255 case InlineMethodAnalyser::IGetVariant(Instruction::IGET_WIDE):
258 case InlineMethodAnalyser::IGetVariant(Instruction::IGET_OBJECT):
261 case InlineMethodAnalyser::IGetVariant(Instruction::IGET_SHORT):
264 case InlineMethodAnalyser::IGetVariant(Instruction::IGET_CHAR):
267 case InlineMethodAnalyser::IGetVariant(Instruction::IGET_BYTE):
270 case InlineMethodAnalyser::IGetVariant(Instruction::IGET_BOOLEAN):
324 case InlineMethodAnalyser::IPutVariant(Instruction::IPUT):
327 case InlineMethodAnalyser::IPutVariant(Instruction::IPUT_WIDE):
330 case InlineMethodAnalyser::IPutVariant(Instruction::IPUT_OBJECT)
[all...] |
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 8 ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips32r2.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 8 dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips3-wrong-error.s | 9 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
13 ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
14 ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15 lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
16 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
17 sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
18 scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[all...] |
| invalid-mips5.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips4.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreLowerThreadLocal.cpp | 77 static Instruction *
78 createReplacementInstr(ConstantExpr *CE, Instruction *Instr) {
82 case Instruction::GetElementPtr: {
85 return dyn_cast<Instruction>(Builder.CreateInBoundsGEP(
89 case Instruction::Add:
90 case Instruction::Sub:
91 case Instruction::Mul:
92 case Instruction::UDiv:
93 case Instruction::SDiv:
94 case Instruction::FDiv
[all...] |
| /art/compiler/dex/ |
| local_value_numbering_test.cc | 46 Instruction::Code opcode;
247 DEF_IGET(Instruction::IGET, 0u, 10u, 0u),
248 DEF_IGET(Instruction::IGET, 1u, 10u, 0u),
249 DEF_INVOKE1(Instruction::INVOKE_VIRTUAL, 11u),
250 DEF_IGET(Instruction::IGET, 2u, 10u, 0u),
271 DEF_IGET(Instruction::IGET_OBJECT, 0u, 10u, 0u),
272 DEF_IPUT(Instruction::IPUT_OBJECT, 1u, 11u, 0u), // May alias.
273 DEF_IGET(Instruction::IGET_OBJECT, 2u, 10u, 0u),
274 DEF_IGET(Instruction::IGET, 3u, 0u, 1u),
275 DEF_IGET(Instruction::IGET, 4u, 2u, 1u)
[all...] |
| /dalvik/dx/tests/032-bb-live-code/ |
| info.txt | 3 to. There is at least one example of each instruction which allows
4 flow to the subsequent instruction, and all forks of each conditional
|
| /dalvik/dx/tests/112-dex-return-jsr-result/ |
| info.txt | 5 goto instruction to be interposed between an invoke instruction and
|
