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  /external/smali/dexlib2/src/main/java/org/jf/dexlib2/iface/instruction/formats/
Instruction22b.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.NarrowLiteralInstruction;
35 import org.jf.dexlib2.iface.instruction.TwoRegisterInstruction;
Instruction22c.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.ReferenceInstruction;
35 import org.jf.dexlib2.iface.instruction.TwoRegisterInstruction;
Instruction22cs.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.FieldOffsetInstruction;
35 import org.jf.dexlib2.iface.instruction.TwoRegisterInstruction;
Instruction22s.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.NarrowLiteralInstruction;
35 import org.jf.dexlib2.iface.instruction.TwoRegisterInstruction;
Instruction22t.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.OffsetInstruction;
35 import org.jf.dexlib2.iface.instruction.TwoRegisterInstruction;
Instruction31c.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.OneRegisterInstruction;
35 import org.jf.dexlib2.iface.instruction.ReferenceInstruction;
Instruction31i.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.NarrowLiteralInstruction;
35 import org.jf.dexlib2.iface.instruction.OneRegisterInstruction;
Instruction31t.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.OffsetInstruction;
35 import org.jf.dexlib2.iface.instruction.OneRegisterInstruction;
Instruction35c.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.FiveRegisterInstruction;
35 import org.jf.dexlib2.iface.instruction.ReferenceInstruction;
Instruction35mi.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.FiveRegisterInstruction;
35 import org.jf.dexlib2.iface.instruction.InlineIndexInstruction;
Instruction35ms.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.FiveRegisterInstruction;
35 import org.jf.dexlib2.iface.instruction.VtableIndexInstruction;
Instruction3rc.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.ReferenceInstruction;
35 import org.jf.dexlib2.iface.instruction.RegisterRangeInstruction;
Instruction3rmi.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.InlineIndexInstruction;
35 import org.jf.dexlib2.iface.instruction.RegisterRangeInstruction;
Instruction3rms.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.RegisterRangeInstruction;
35 import org.jf.dexlib2.iface.instruction.VtableIndexInstruction;
Instruction51l.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.OneRegisterInstruction;
35 import org.jf.dexlib2.iface.instruction.WideLiteralInstruction;
  /external/v8/src/compiler/arm/
instruction-codes-arm.h 13 // Most opcodes specify a single instruction.
65 // Addressing modes represent the "shape" of inputs to an instruction.
67 // are encoded into the InstructionCode of the instruction and tell the
  /external/v8/src/compiler/arm64/
instruction-codes-arm64.h 13 // Most opcodes specify a single instruction.
87 // Addressing modes represent the "shape" of inputs to an instruction.
89 // are encoded into the InstructionCode of the instruction and tell the
  /external/v8/src/compiler/ia32/
instruction-codes-ia32.h 13 // Most opcodes specify a single instruction.
55 // Addressing modes represent the "shape" of inputs to an instruction.
57 // are encoded into the InstructionCode of the instruction and tell the
  /external/vixl/examples/
custom-disassembler.h 45 virtual void VisitAddSubShifted(const Instruction* instr);
48 virtual void AppendRegisterNameToOutput(const Instruction* instr,
51 virtual void AppendCodeRelativeCodeAddressToOutput(const Instruction* instr,
  /external/llvm/lib/IR/
Instructions.cpp 10 // This file implements all of the non-inline methods for the LLVM instruction
34 Instruction *II(getInstruction());
88 : Instruction(PN.getType(), Instruction::PHI,
182 Instruction *InsertBefore)
183 : Instruction(RetTy, Instruction::LandingPad, nullptr, 0, InsertBefore) {
190 : Instruction(RetTy, Instruction::LandingPad, nullptr, 0, InsertAtEnd) {
195 : Instruction(LP.getType(), Instruction::LandingPad
    [all...]
  /art/compiler/dex/
mir_optimization.cc 78 case Instruction::CONST_4:
79 case Instruction::CONST_16:
80 case Instruction::CONST:
83 case Instruction::CONST_HIGH16:
86 case Instruction::CONST_WIDE_16:
87 case Instruction::CONST_WIDE_32:
90 case Instruction::CONST_WIDE:
93 case Instruction::CONST_WIDE_HIGH16:
149 if ((mir->dalvikInsn.opcode == Instruction::MOVE_RESULT) ||
150 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) |
    [all...]
  /art/compiler/optimizing/
code_generator_mips64.h 158 void HandleFieldSet(HInstruction* instruction, const FieldInfo& field_info);
159 void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
190 void HandleFieldSet(HInstruction* instruction, const FieldInfo& field_info);
191 void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
192 void GenerateImplicitNullCheck(HNullCheck* instruction);
193 void GenerateExplicitNullCheck(HNullCheck* instruction);
194 void GenerateTestAndBranch(HInstruction* instruction,
217 void Move(HInstruction* instruction, Location location, HInstruction* move_for) OVERRIDE;
276 HInstruction* instruction,
nodes.h 76 void AddInstruction(HInstruction* instruction);
77 void RemoveInstruction(HInstruction* instruction);
79 // Insert `instruction` before/after an existing instruction `cursor`.
80 void InsertInstructionBefore(HInstruction* instruction, HInstruction* cursor);
81 void InsertInstructionAfter(HInstruction* instruction, HInstruction* cursor);
83 // Return true if this list contains `instruction`.
84 bool Contains(HInstruction* instruction) const;
87 // this instruction list and false otherwise. Abort if none
185 // Inline this graph in `outer_graph`, replacing the given `invoke` instruction
    [all...]
  /art/disassembler/
disassembler_arm64.h 36 MapCodeAddress(0, reinterpret_cast<const vixl::Instruction*>(options->base_address_));
41 void AppendRegisterNameToOutput(const vixl::Instruction* instr,
45 void VisitLoadLiteral(const vixl::Instruction* instr) OVERRIDE;
48 void VisitLoadStoreUnsignedOffset(const vixl::Instruction* instr) OVERRIDE;
  /art/runtime/arch/arm/
fault_handler_arm.cc 41 // Get the size of a thumb2 instruction in bytes.
90 // Work out the return PC. This will be the address of the instruction
91 // following the faulting ldr/str instruction. This is in thumb mode so
92 // the instruction might be a 16 or 32 bit one. Also, the GC map always
95 // Need to work out the size of the instruction that caused the exception.
114 // the load/store instruction that might cause the fault. However the mapping table has
118 // Need to work out the size of the instruction that caused the exception.
130 // A suspend check is done using the following instruction sequence:
132 // .. some intervening instruction
154 // Second instruction is not good, not ours
    [all...]

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