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  /external/llvm/test/Transforms/ConstProp/
phi.ll 1 ; This is a basic sanity check for constant propagation. The add instruction
  /external/llvm/test/Verifier/
dominates.ll 7 ; CHECK: Instruction does not dominate all uses!
23 ; CHECK: Instruction does not dominate all uses!
41 ; CHECK: Instruction does not dominate all uses!
54 ; CHECK: Instruction does not dominate all uses!
  /external/llvm/utils/TableGen/
PseudoLoweringEmitter.cpp 37 CodeGenInstruction Source; // The source pseudo instruction definition.
38 CodeGenInstruction Dest; // The destination instruction to lower to.
69 // FIXME: This pass currently can only expand a pseudo to a single instruction.
126 // of arguments for the instruction it references.
128 assert(Dag && "Missing result instruction in pseudo expansion!");
136 if (!Operator->isSubClassOf("Instruction"))
138 "' is not an instruction!");
144 "' cannot be another pseudo instruction!");
163 // argument in the source instruction, in either the (outs) or (ins) list.
175 // We've already handled constant values. Just map instruction operand
    [all...]
X86DisassemblerShared.h 32 /// instruction each possible value of the ModR/M byte corresponds to. Once
33 /// this information is known, we have narrowed down to a single instruction.
39 /// Specifies which set of ModR/M->instruction tables to look at
45 /// Specifies which opcode->instruction tables to look at given
  /external/mesa3d/src/gallium/drivers/nv30/
nv30_vertprog.h 4 /* Vertex programs instruction set
16 * - Only one INPUT can be accessed per-instruction (move extras into TEMPs)
17 * - Only one CONST can be accessed per-instruction (move extras into TEMPs)
24 * ARL instruction is set to TEMP <n> (The temp isn't actually written).
36 * Only one address register can be accessed per instruction.
39 * execution of an instruction is enabled by setting COND_TEST_ENABLE, and
47 * layout. The destination instruction ID (IADDR) overlaps a source field.
48 * Instruction ID's seem to be numbered based on the UPLOAD_FROM_ID FIFO
57 * executed instruction is determined by the PROGRAM_START_ID FIFO command.
  /external/mockito/cglib-and-asm/src/org/mockito/asm/tree/
LineNumberNode.java 38 * instruction nodes in order to be inserted in an instruction list.
51 * The first instruction corresponding to this line number.
60 * @param start the first instruction corresponding to this line number.
  /external/proguard/src/proguard/optimize/info/
BackwardBranchMarker.java 25 import proguard.classfile.instruction.*;
26 import proguard.classfile.instruction.visitor.InstructionVisitor;
41 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
DotClassMarker.java 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
46 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
InstanceofClassMarker.java 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
46 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
InstantiationClassMarker.java 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
46 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
MethodInvocationMarker.java 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
46 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
SuperInvocationMarker.java 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
47 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
VariableUsageMarker.java 26 import proguard.classfile.instruction.*;
27 import proguard.classfile.instruction.visitor.InstructionVisitor;
82 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
  /external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/Format/
UnresolvedOdexInstructionMethodItem.java 40 @Nonnull UnresolvedOdexInstruction instruction) {
41 super(methodDef, codeAddress, instruction);
50 writer.write("#Replaced unresolvable odex instruction with a throw\n");
52 writeRegister(writer, instruction.objectRegisterNum);
  /external/smali/dexlib2/src/main/java/org/jf/dexlib2/builder/
BuilderInstruction.java 36 import org.jf.dexlib2.iface.instruction.Instruction;
42 public abstract class BuilderInstruction implements Instruction {
65 throw new IllegalStateException("Cannot get the location of an instruction that hasn't been added to a " +
  /external/smali/dexlib2/src/main/java/org/jf/dexlib2/dexbacked/instruction/
DexBackedInstruction.java 32 package org.jf.dexlib2.dexbacked.instruction;
37 import org.jf.dexlib2.iface.instruction.Instruction;
43 public abstract class DexBackedInstruction implements Instruction {
60 public static Instruction readFrom(@Nonnull DexReader reader) {
69 Instruction instruction = buildInstruction(reader.dexBuf, opcode, reader.getOffset()); local
70 reader.moveRelative(instruction.getCodeUnits()*2);
71 return instruction;
  /external/smali/dexlib2/src/test/java/org/jf/dexlib2/analysis/
CustomMethodInlineTableTest.java 40 import org.jf.dexlib2.iface.instruction.Instruction;
41 import org.jf.dexlib2.iface.instruction.formats.Instruction35c;
47 import org.jf.dexlib2.immutable.instruction.ImmutableInstruction;
48 import org.jf.dexlib2.immutable.instruction.ImmutableInstruction10x;
49 import org.jf.dexlib2.immutable.instruction.ImmutableInstruction35mi;
76 Instruction deodexedInstruction = methodAnalyzer.getInstructions().get(0);
103 Instruction deodexedInstruction = methodAnalyzer.getInstructions().get(0);
130 Instruction deodexedInstruction = methodAnalyzer.getInstructions().get(0);
  /external/v8/src/arm/
constants-arm.h 17 // Use UDF, the permanently undefined instruction.
122 // Instruction objects are pointers to 32bit values, and provide methods to
162 // Instruction encoding bits and masks.
169 A = 1 << 21, // Accumulate in multiply instruction (or not).
196 // Instruction bit masks.
199 kRdMask = 15 << 12, // In str instruction.
211 // Addressing modes and instruction variants.
409 // Instruction abstraction.
411 // The class Instruction enables access to individual fields defined in the ARM
412 // architecture instruction set encoding as described in figure A3-1
    [all...]
  /external/v8/src/compiler/
code-generator-impl.h 11 #include "src/compiler/instruction.h"
22 // Converts InstructionOperands from a given instruction to
28 InstructionOperandConverter(CodeGenerator* gen, Instruction* instr)
116 Instruction* instr_;
  /external/v8/test/cctest/
test-fuzz-arm64.cc 36 // 43 million = ~1% of the instruction space.
43 Instruction buffer[kInstructionSize];
55 // 9 million = ~0.2% of the instruction space.
63 Instruction buffer[kInstructionSize];
  /external/valgrind/none/tests/mips64/
rotate_swap.c 3 #define TESTINST_DROTR(instruction, in, SA) \
9 instruction" $t0, $t1, "#SA "\n\t" \
16 instruction, (long long) in, out, SA); \
19 #define TESTINST_DROTRV(instruction, in, SA) \
26 instruction" $t0, $t1, $t2" "\n\t" \
33 instruction, (long long) in, out, SA); \
36 #define TESTINST_DSWAP(instruction, in) \
43 instruction" $t0, $t1" "\n\t" \
50 instruction, (long long) in, out); \
  /external/valgrind/none/tests/ppc64/
test_touch_tm.c 7 * For now, only the tbegin instruction does anything in valgrind.
  /external/valgrind/none/tests/x86/
faultstatus.stderr.exp 6 Test 5: disInstr: unhandled instruction bytes: 0x........ 0x........ 0x........ 0x........
  /frameworks/base/docs/html/ndk/guides/
cpu-features.jd 35 insert an instruction to import the {@code android/cpufeatures} module. For example:
96 <dd>Indicates that the device's CPU supports the VFPv2 instruction set. Most ARMv6 CPUs support
97 this instruction set.</dd>
100 <dd>Indicates that the device's CPU supports the ARMv7-A instruction set as supported by the
101 <a href="{@docRoot}ndk/guides/abis.html#v7a">armeabi-v7a</a> ABI. This instruction set supports both
103 FPU instruction-set extension.</dd>
106 <dd>Indicates that the device's CPU supports the VFPv3 hardware FPU instruction-set extension.
107 <p>This value is equivalent to the {@code VFPv3-D16} instruction set, which provides provides only
116 <dd>Indicates that the device's CPU supports the ARM Advanced SIMD (NEON) vector instruction set
126 instruction set. Also part of the VFPv4 specification.</dd
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  /prebuilts/misc/android-mips/gdbserver/
README.txt 1 Build instruction:

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