| /prebuilts/misc/android-mips64/gdbserver64/ |
| README.txt | 1 Build instruction:
|
| /prebuilts/misc/android-x86_64/gdbserver64/ |
| README.txt | 1 Build instruction:
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetTransformInfo.cpp | 118 case Instruction::GetElementPtr:
125 case Instruction::And:
128 case Instruction::Add:
129 case Instruction::Or:
130 case Instruction::Xor:
133 case Instruction::Sub:
134 case Instruction::Mul:
135 case Instruction::Shl:
136 case Instruction::LShr:
137 case Instruction::AShr
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 29 Instruction &CxtI) {
60 if (I->getOpcode() == Instruction::LShr && !I->isExact()) {
65 if (I->getOpcode() == Instruction::Shl && !I->hasNoUnsignedWrap()) {
129 Instruction &CxtI) {
168 Instruction *InstCombiner::visitMul(BinaryOperator &I) {
261 if (Instruction *R = FoldOpIntoSelect(I, SI))
265 if (Instruction *NV = FoldOpIntoPhi(I))
299 (BO->getOpcode() != Instruction::UDiv &&
300 BO->getOpcode() != Instruction::SDiv)) {
307 (BO->getOpcode() == Instruction::UDiv |
[all...] |
| /prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/x86_64-linux-gnu/aarch64-linux-android/include/ |
| dis-asm.h | 23 The opcode library (libopcodes.a) provides instruction decoders for
24 a large variety of instruction sets, callable with an identical
25 interface, for making instruction-processing programs more independent
26 of the instruction set being processed. */
42 dis_noninsn, /* Not a valid instruction. */
43 dis_nonbranch, /* Not a branch instruction. */
48 dis_dref, /* Data reference instruction. */
49 dis_dref2 /* Two data references in instruction. */
52 /* This struct is passed into the instruction decoding routine,
55 for passing information into the instruction decoders (such as th
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64LoadStoreOptimizer.cpp | 61 // with the current instruction into a load/store pair.
62 // Return the matching instruction if one is found, else MBB->end().
63 // If a matching instruction is found, MergeForward is set to true if the
64 // merge is to remove the first instruction and replace the second with
74 // Merge the two instructions indicated into a single pair-wise instruction.
75 // If MergeForward is true, erase the first instruction and fold its
76 // operation into the second. If false, the reverse. Return the instruction
77 // following the first instruction (which may change during processing).
85 // Scan the instruction list to find a base register update that can
86 // be combined with the current instruction (a load or store) usin
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| InsnFormat.java | 29 * Base class for all instruction format handlers. Instruction format
37 * dump, of the given instruction. The instruction must be of this
40 * @param insn {@code non-null;} the instruction
67 * Returns the string form of the arguments to the given instruction.
68 * The instruction must be of this instance's format. If the instruction
74 * @param insn {@code non-null;} the instruction
80 * Returns the associated comment for the given instruction, if any
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_emit_nv50.cpp | 38 virtual bool emitInstruction(Instruction *);
40 virtual uint32_t getMinEncodingSize(const Instruction *) const;
59 void emitFlagsRd(const Instruction *);
60 void emitFlagsWr(const Instruction *);
66 void setAReg16(const Instruction *, int s);
67 void setImmediate(const Instruction *, int s);
70 void setDst(const Instruction *, int d);
71 void setSrcFileBits(const Instruction *, int enc);
72 void setSrc(const Instruction *, unsigned int s, int slot);
74 void emitForm_MAD(const Instruction *);
[all...] |
| nv50_ir.cpp | 101 Instruction *insn = src->value->getUniqueInsn();
173 if (!insn || !insn->bb) // Unbound instruction ?
180 Instruction *insn = (*it)->getInsn();
276 Instruction *insn = getInsn();
552 void Instruction::init()
582 Instruction::Instruction()
593 Instruction::Instruction(Function *fn, operation opr, DataType ty)
603 Instruction::~Instruction(
[all...] |
| nv50_ir_inlines.h | 176 Instruction *Value::getInsn() const
181 Instruction *Value::getUniqueInsn() const
207 inline bool Instruction::constrainedDefs() const
212 Value *Instruction::getIndirect(int s, int dim) const
217 Value *Instruction::getPredicate() const
222 void Instruction::setFlagsDef(int d, Value *val)
236 void Instruction::setFlagsSrc(int s, Value *val)
252 CmpInstruction *Instruction::asCmp()
259 const CmpInstruction *Instruction::asCmp() const
266 FlowInstruction *Instruction::asFlow(
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| TailRecursionElimination.cpp | 11 // by a return instruction with a branch to the entry of the function, creating
40 // return instruction. It's possible that there could be a jump between
104 CallInst *FindTRECandidate(Instruction *I,
120 bool CanMoveAboveCall(Instruction *I, CallInst *CI);
121 Value *CanTransformAccumulatorRecursion(Instruction *I, CallInst *CI);
189 Instruction *I = cast<Instruction>(U->getUser());
192 case Instruction::Call:
193 case Instruction::Invoke: {
205 case Instruction::Load:
[all...] |
| DeadStoreElimination.cpp | 110 /// DeleteDeadInstruction - Delete this instruction. Before we do, go through
111 /// and zero out all the operands of this instruction. If any of them become
116 static void DeleteDeadInstruction(Instruction *I,
120 SmallVector<Instruction*, 32> NowDeadInsts;
125 // Before we touch this instruction, remove it from memdep!
127 Instruction *DeadInst = NowDeadInsts.pop_back_val();
130 // This instruction is dead, zap it, in stages. Start by removing it from
142 if (Instruction *OpI = dyn_cast<Instruction>(Op))
154 /// hasMemoryWrite - Does this instruction write some memory? This only return
[all...] |
| /art/runtime/interpreter/ |
| interpreter_common.h | 98 const Instruction* inst, uint16_t inst_data, JValue* result);
103 static inline bool DoInvoke(Thread* self, ShadowFrame& shadow_frame, const Instruction* inst,
130 const Instruction* inst, uint16_t inst_data,
161 bool DoFieldGet(Thread* self, ShadowFrame& shadow_frame, const Instruction* inst,
167 bool DoIGetQuick(ShadowFrame& shadow_frame, const Instruction* inst, uint16_t inst_data)
174 bool DoFieldPut(Thread* self, const ShadowFrame& shadow_frame, const Instruction* inst,
180 bool DoIPutQuick(const ShadowFrame& shadow_frame, const Instruction* inst, uint16_t inst_data)
285 bool DoFilledNewArray(const Instruction* inst, const ShadowFrame& shadow_frame,
288 // Handles packed-switch instruction.
289 // Returns the branch offset to the next instruction to execute
[all...] |
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc_optimize.c | 173 memcpy(&o->Instruction, &i->Instruction, sizeof(o->Instruction));
204 op_commutes(current->FullInstruction.Instruction.Opcode) &&
205 current->FullInstruction.Instruction.Saturate == next->FullInstruction.Instruction.Saturate &&
206 next->FullInstruction.Instruction.Opcode == TGSI_OPCODE_MOV &&
214 next->FullInstruction.Instruction.Opcode = TGSI_OPCODE_NOP;
219 op_neutral_element(current->FullInstruction.Instruction.Opcode));
228 op_commutes(current->FullInstruction.Instruction.Opcode) &
[all...] |
| /external/valgrind/none/tests/mips32/ |
| branches.c | 114 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \
121 instruction" $" #RS ", $" #RT ", end"instruction#RDval"\n\t" \
124 "end"instruction#RDval":\n\t" \
131 printf(instruction" :: %d, RSval: %d, RTval: %d\n", \
135 #define TESTINST5(instruction, RDval, RSval, RD, RS) \
141 instruction" $" #RS ", end"instruction#RDval"\n\t" \
144 "end"instruction#RDval":\n\t" \
151 printf(instruction" :: %d, RSval: %d\n",
[all...] |
| /external/llvm/include/llvm/IR/ |
| PatternMatch.h | 24 // This is primarily useful to things like the instruction combiner, but can
71 /// \brief Matches any compare instruction and ignore it.
298 /// \brief Match an instruction, capturing it if we match.
299 inline bind_ty<Instruction> m_Instruction(Instruction *&I) { return I; }
434 inline BinaryOp_match<LHS, RHS, Instruction::Add> m_Add(const LHS &L,
436 return BinaryOp_match<LHS, RHS, Instruction::Add>(L, R);
440 inline BinaryOp_match<LHS, RHS, Instruction::FAdd> m_FAdd(const LHS &L,
442 return BinaryOp_match<LHS, RHS, Instruction::FAdd>(L, R);
446 inline BinaryOp_match<LHS, RHS, Instruction::Sub> m_Sub(const LHS &L
[all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| LoopVectorize.cpp | 162 "force-target-instruction-cost", cl::init(0), cl::Hidden,
164 "an instruction to a single constant value. Mostly "
211 VectorizationReport(Instruction *I = nullptr)
261 // Widen each instruction in the old loop to a new one in the new loop.
280 /// originated from one scalar instruction.
290 /// Returns the last check instruction and the first check instruction in the
292 std::pair<Instruction *, Instruction *> addStrideCheck(Instruction *Loc)
[all...] |
| /art/compiler/optimizing/ |
| reference_type_propagation.cc | 108 // If that's the case insert an HBoundType instruction to bound the type of `x`
119 // The instruction simplifier has transformed:
141 // over phis. Non-phis instruction whose type is already known do
260 LOG(FATAL) << "Invalid instruction (should not get here)";
296 // Re-computes and updates the nullability of the instruction. Returns whether or
318 HInstruction* instruction = worklist_.Pop(); local
319 if (UpdateNullability(instruction) || UpdateReferenceTypeInfo(instruction)) {
320 AddDependentInstructionsToWorklist(instruction);
325 void ReferenceTypePropagation::AddToWorklist(HInstruction* instruction) {
[all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| basic-a64-unpredictable.txt | 10 #CHECK: warning: potentially undefined instruction encoding
15 #CHECK: warning: potentially undefined instruction encoding
23 #CHECK: warning: potentially undefined instruction encoding
27 #CHECK: warning: potentially undefined instruction encoding
35 #CHECK: warning: potentially undefined instruction encoding
39 #CHECK: warning: potentially undefined instruction encoding
49 # CHECK: warning: potentially undefined instruction encoding
54 # CHECK: warning: potentially undefined instruction encoding
59 # CHECK: warning: potentially undefined instruction encoding
70 # CHECK: warning: potentially undefined instruction encodin
[all...] |
| /dalvik/dx/src/com/android/dx/ssa/ |
| SsaInsn.java | 27 * An instruction in SSA form
192 * instruction, or null if no local variable assignment occurs. This
210 * used as sources for this instruction.
224 * @return {@code non-null;} a ROP representation of this instruction, with
245 * move-exception) instruction
252 * @return true if this is a move-exception instruction.
260 * @return true if this instruction can throw.
276 * Any non-phi move instruction
277 * @param insn {@code non-null;} the instruction to visit
283 * @param insn {@code non-null;} the instruction to visi
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| SsaInsn.java | 23 * An instruction in SSA form
188 * instruction, or null if no local variable assignment occurs. This
206 * used as sources for this instruction.
220 * @return {@code non-null;} a ROP representation of this instruction, with
241 * move-exception) instruction
248 * @return true if this is a move-exception instruction.
256 * @return true if this instruction can throw.
272 * Any non-phi move instruction
273 * @param insn {@code non-null;} the instruction to visit
279 * @param insn {@code non-null;} the instruction to visi
[all...] |
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/ |
| InlineMethodResolver.java | 36 import org.jf.dexlib2.iface.instruction.InlineIndexInstruction;
37 import org.jf.dexlib2.iface.instruction.VariableRegisterInstruction;
73 @Nonnull public abstract Method resolveExecuteInline(@Nonnull AnalyzedInstruction instruction);
101 InlineIndexInstruction instruction = (InlineIndexInstruction)analyzedInstruction.instruction; local
102 int inlineIndex = instruction.getInlineIndex();
171 InlineIndexInstruction instruction = (InlineIndexInstruction)analyzedInstruction.instruction; local
172 int inlineIndex = instruction.getInlineIndex();
179 int parameterCount = ((VariableRegisterInstruction)instruction).getRegisterCount()
[all...] |
| /external/smali/dexlib2/src/test/java/org/jf/dexlib2/writer/ |
| JumboStringConversionTest.java | 42 import org.jf.dexlib2.builder.instruction.BuilderInstruction10x;
43 import org.jf.dexlib2.builder.instruction.BuilderInstruction21c;
47 import org.jf.dexlib2.iface.instruction.Instruction;
48 import org.jf.dexlib2.iface.instruction.ReferenceInstruction;
49 import org.jf.dexlib2.iface.instruction.formats.Instruction21c;
52 import org.jf.dexlib2.immutable.instruction.ImmutableInstruction10x;
106 List<? extends Instruction> instructions = Lists.newArrayList(impl.getInstructions());
127 final List<Instruction> instructions = Lists.newArrayList();
158 @Nonnull @Override public Iterable<? extends Instruction> getInstructions()
[all...] |
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/writer/ |
| DexWriter.java | 44 import org.jf.dexlib2.builder.instruction.BuilderInstruction31c;
51 import org.jf.dexlib2.iface.instruction.Instruction;
52 import org.jf.dexlib2.iface.instruction.OneRegisterInstruction;
53 import org.jf.dexlib2.iface.instruction.ReferenceInstruction;
54 import org.jf.dexlib2.iface.instruction.formats.*;
[all...] |
| /dalvik/docs/ |
| dalvik-constraints.html | 201 The index of instruction <code>n+1</code> must equal the index of
202 instruction <code>n</code> plus the length of instruction
217 The last instruction in the <code>insns</code> array must end at index
247 All targets of a <code>packed-switch</code> instruction must be
263 All targets of a <code>sparse-switch</code> instruction must be
383 instruction must be a valid index into the method constant pool. The
400 instruction must be a valid index into the method constant pool.
450 instruction must be less than <code>256</code>.
464 The <code>new</code> instruction must not refer to array classes
[all...] |
