| /external/llvm/test/MC/ARM/ |
| obsolete-v8.s | 4 @ CHECK: instruction requires: armv7 or earlier
7 @ CHECK: instruction requires: armv7 or earlier
|
| vmov-vmvn-illegal-cases.s | 4 @ CHECK: error: invalid operand for instruction
6 @ CHECK: error: invalid operand for instruction
8 @ CHECK: error: invalid operand for instruction
10 @ CHECK: error: invalid operand for instruction
13 @ CHECK: error: invalid operand for instruction
15 @ CHECK: error: invalid operand for instruction
17 @ CHECK: error: invalid operand for instruction
19 @ CHECK: error: invalid operand for instruction
|
| /external/llvm/test/MC/Disassembler/SystemZ/ |
| trunc-01.txt | 2 # Every instruction must be at least two bytes long.
3 # CHECK: warning: invalid instruction encoding
|
| trunc-02.txt | 2 # If the top bits are 0b10, the instruction must be 4 bytes long.
3 # CHECK: warning: invalid instruction encoding
|
| /external/llvm/test/MC/Disassembler/X86/ |
| invalid-VEX-vvvv.txt | 1 # RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 2>&1 | grep "invalid instruction encoding"
3 # This instruction would decode as movmskps if the vvvv field in the VEX prefix was all 1s.
|
| missing-sib.txt | 1 # RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 2>&1 | grep "invalid instruction encoding"
3 # This instruction would decode as jmp32m if it didn't run out of bytes
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips2-wrong-error.s | 9 ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11 ldc3 $29,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
13 sc $t7,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
14 sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15 sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
16 sdc3 $12,5835($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips2.s | 8 bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bc1fl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bc1tl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 beql $14,$s3,12544 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 bgezl $4,-6858 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 bgtzl $10,-3738 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 blezl $6,2974 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 bltzall $6,488 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips4-wrong-error.s | 9 bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
13 scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
14 sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15 sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
16 sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips3-wrong-error.s | 9 dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11 ldl $t8,-4167($t8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 ldr $t2,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
13 lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
14 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15 scd $t3,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
16 sd $t0,5835($a6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
17 sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
18 sdr $a7,-20423($t0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[all...] |
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32-wrong-error.s | 9 bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| invalid-mips32.s | 8 bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips1-wrong-error.s | 8 bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
9 bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11 lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
13 swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
14 lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
[all...] |
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 8 clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips2.s | 8 addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 bc1fl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 bc1tl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 beql $14,$s3,12544 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 bgezl $4,-6858 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips32-wrong-error.s | 9 bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| invalid-mips5-wrong-error.s | 8 abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
9 add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 alnv.ps $f12,$f18,$f30,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
14 bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
[all...] |
| invalid-mips1-wrong-error.s | 8 bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
9 bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11 lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12 swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
13 swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
14 lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
15 lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
16 swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
[all...] |
| /external/llvm/test/MC/R600/ |
| sop1-err.s | 5 // CHECK: error: invalid operand for instruction
8 // CHECK: error: invalid operand for instruction
11 // CHECK: error: invalid operand for instruction
14 // CHECK: error: invalid operand for instruction
17 // CHECK: error: invalid operand for instruction
20 // CHECK: error: invalid operand for instruction
23 // CHECK: error: invalid operand for instruction
26 // CHECK: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/ |
| set-mips-directives-bad.s | 5 # ll instruction using an unsupported architecture so we just check for "error"
13 dadd $2,$2,$2 # CHECK: error: instruction requires a CPU feature not currently enabled
15 ldxc1 $f8,$2($4) # CHECK: error: instruction requires a CPU feature not currently enabled
17 luxc1 $f19,$2($4) # CHECK: error: instruction requires a CPU feature not currently enabled
19 clo $2,$2 # CHECK: error: instruction requires a CPU feature not currently enabled
21 rotr $2,15 # CHECK: error: instruction requires a CPU feature not currently enabled
23 mod $2, $4, $6 # CHECK: error:instruction requires a CPU feature not currently enabled
26 daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
29 daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled
31 daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enable
[all...] |
| /art/compiler/dex/ |
| global_value_numbering_test.cc | 62 Instruction::Code opcode;
135 { bb, static_cast<Instruction::Code>(kMirOpPhi), 0, 0u, 2u, { src1, src2 }, 1, { reg } }
253 } else if (def->opcode == static_cast<Instruction::Code>(kMirOpPhi)) {
552 DEF_UNIQUE_REF(3, Instruction::NEW_INSTANCE, 100u),
553 DEF_IGET(3, Instruction::IGET, 1u, 100u, 0u),
554 DEF_IGET(6, Instruction::IGET, 2u, 100u, 0u), // Same as at the top.
556 DEF_UNIQUE_REF(3, Instruction::NEW_INSTANCE, 200u),
557 DEF_IGET(4, Instruction::IGET, 4u, 200u, 1u),
558 DEF_IGET(6, Instruction::IGET, 5u, 200u, 1u), // Same as at the left side.
560 DEF_UNIQUE_REF(3, Instruction::NEW_INSTANCE, 300u)
[all...] |
| /external/clang/test/CodeGenObjC/ |
| arc-captured-block-var-inlined-layout.m | 20 // CHECK: Inline instruction for block variable layout: 0x0100
21 // CHECK-i386: Inline instruction for block variable layout: 0x0100
26 // CHECK: Inline instruction for block variable layout: 0x0210
27 // CHECK-i386: Inline instruction for block variable layout: 0x0210
34 // CHECK: Inline instruction for block variable layout: 0x0230
35 // CHECK-i386: Inline instruction for block variable layout: 0x0230
44 // CHECK: Inline instruction for block variable layout: 0x0231
45 // CHECK-i386: Inline instruction for block variable layout: 0x0231
56 // CHECK: Inline instruction for block variable layout: 0x0235
57 // CHECK-i386: Inline instruction for block variable layout: 0x023
[all...] |
| /external/proguard/src/proguard/classfile/editor/ |
| CodeAttributeEditor.java | 32 import proguard.classfile.instruction.*;
33 import proguard.classfile.instruction.visitor.InstructionVisitor;
73 /*private*/public Instruction[] preInsertions = new Instruction[ClassConstants.TYPICAL_CODE_LENGTH];
74 /*private*/public Instruction[] replacements = new Instruction[ClassConstants.TYPICAL_CODE_LENGTH];
75 /*private*/public Instruction[] postInsertions = new Instruction[ClassConstants.TYPICAL_CODE_LENGTH];
123 preInsertions = new Instruction[codeLength];
124 replacements = new Instruction[codeLength]
206 CompositeInstruction instruction = local
254 CompositeInstruction instruction = local
302 CompositeInstruction instruction = local
648 Instruction instruction = InstructionFactory.create(oldCode, oldOffset); local
730 Instruction instruction = InstructionFactory.create(oldCode, oldOffset); local
1201 Instruction instruction = instructions[index]; local
1244 Instruction instruction = instructions[index]; local
[all...] |
| /art/compiler/dex/quick/mips/ |
| fp_mips.cc | 26 void MipsMir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest,
36 case Instruction::ADD_FLOAT_2ADDR:
37 case Instruction::ADD_FLOAT:
40 case Instruction::SUB_FLOAT_2ADDR:
41 case Instruction::SUB_FLOAT:
44 case Instruction::DIV_FLOAT_2ADDR:
45 case Instruction::DIV_FLOAT:
48 case Instruction::MUL_FLOAT_2ADDR:
49 case Instruction::MUL_FLOAT:
52 case Instruction::REM_FLOAT_2ADDR
[all...] |
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/dexbacked/raw/ |
| CodeItem.java | 38 import org.jf.dexlib2.dexbacked.instruction.DexBackedInstruction;
40 import org.jf.dexlib2.iface.instruction.*;
41 import org.jf.dexlib2.iface.instruction.formats.*;
121 Instruction instruction = DexBackedInstruction.readFrom(reader); local
123 // if we read past the end of the instruction list
125 out.annotateTo(end, "truncated instruction");
128 switch (instruction.getOpcode().format) {
130 annotateInstruction10x(out, instruction);
133 annotateInstruction35c(out, (Instruction35c)instruction);
[all...] |
