| /art/disassembler/ |
| disassembler_arm64.cc | 43 const vixl::Instruction* instr,
60 void CustomDisassembler::VisitLoadLiteral(const vixl::Instruction* instr) {
91 void CustomDisassembler::VisitLoadStoreUnsignedOffset(const vixl::Instruction* instr) {
103 const vixl::Instruction* instr = reinterpret_cast<const vixl::Instruction*>(begin);
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| /external/google-breakpad/src/processor/ |
| fast_source_line_resolver_unittest.cc | 215 frame.instruction = 0x1000;
241 frame.instruction = 0x800;
248 frame.instruction = 0x1280;
259 frame.instruction = 0x1380;
270 frame.instruction = 0x2000;
277 frame.instruction = 0x3d3f;
282 frame.instruction = 0x3e9f;
292 // Regardless of which instruction evaluation takes place at, it
301 frame.instruction = 0x3d40;
317 frame.instruction = 0x3d41
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| AliasSetTracker.h | 114 std::vector<AssertingVH<Instruction> > UnknownInsts;
149 Instruction *getUnknownInst(unsigned i) const {
251 void addUnknownInst(Instruction *I, AliasAnalysis &AA);
252 void removeUnknownInst(AliasSetTracker &AST, Instruction *I) {
271 bool aliasesUnknownInst(Instruction *Inst, AliasAnalysis &AA) const;
313 /// instructions to the alias sets. Adding a new instruction can result in
316 /// 1. If the instruction doesn't alias any other sets, create a new set.
317 /// 2. If the instruction aliases exactly one set, add it to the set
318 /// 3. If the instruction aliases multiple sets, merge the sets, and add
319 /// the instruction to the result
[all...] |
| CaptureTracking.h | 21 class Instruction;
38 /// instruction are considered. This routine can be expensive, so consider
43 /// or not. Captures by the provided instruction are considered if the
46 bool StoreCaptures, const Instruction *I,
63 /// U->getUser() is always an Instruction.
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| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.h | 33 // This utility class tracks the length of a stackmap instruction's 'shadow'.
39 // of instruction bytes output since the last stackmap. Only if there are too
40 // few instruction bytes to cover the shadow are NOPs used for padding.
65 // recently encountered STACKMAP instruction.
77 // This helper function invokes the SMShadowTracker on each instruction before
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| /external/llvm/test/MC/Disassembler/ARM/ |
| invalid-thumb-MSR-MClass.txt | 9 # CHECK: warning: invalid instruction encoding
18 # CHECK: warning: potentially undefined instruction encoding
23 # CHECK: warning: potentially undefined instruction encoding
28 # CHECK-V7M: warning: potentially undefined instruction encoding
33 # CHECK: warning: invalid instruction encoding
|
| /external/llvm/test/MC/R600/ |
| vop2-err.s | 9 // CHECK: error: invalid operand for instruction
17 // CHECK: error: invalid operand for instruction
21 // CHECK: error: invalid operand for instruction
29 // CHECK: error: invalid operand for instruction
33 // CHECK: error: invalid operand for instruction
|
| /external/proguard/src/proguard/optimize/ |
| DuplicateInitializerInvocationFixer.java | 29 import proguard.classfile.instruction.*;
30 import proguard.classfile.instruction.visitor.InstructionVisitor;
98 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
110 Instruction extraInstruction =
|
| TailRecursionSimplifier.java | 29 import proguard.classfile.instruction.*;
30 import proguard.classfile.instruction.visitor.InstructionVisitor;
137 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction)
139 // Copy the instruction.
140 codeAttributeComposer.appendInstruction(offset, instruction);
158 // Is the next instruction a return?
162 Instruction nextInstruction =
195 // The original return instruction will be
217 // Copy the instruction
[all...] |
| /external/llvm/lib/IR/ |
| Constants.cpp | 328 case Instruction::UDiv:
329 case Instruction::SDiv:
330 case Instruction::FDiv:
331 case Instruction::URem:
332 case Instruction::SRem:
333 case Instruction::FRem:
433 if (CE->getOpcode() == Instruction::Sub) {
437 LHS->getOpcode() == Instruction::PtrToInt &&
438 RHS->getOpcode() == Instruction::PtrToInt &&
[all...] |
| /external/lldb/source/Plugins/UnwindAssembly/InstEmulation/ |
| UnwindAssemblyInstEmulation.cpp | 45 // The the instruction emulation subclass setup the unwind plan for the
46 // first instruction.
95 Instruction *inst = inst_list.GetInstructionAtIndex (0).get();
98 // Make a copy of the current instruction Row and save it in m_curr_row
113 bool last_instruction_restored_return_addr_reg = false; // re-install the prologue row of CFI if the next instruction is a branch immediate
120 // quick reference during instruction parsing.
129 // quick reference during instruction parsing.
157 // Were there any changes to the CFI while evaluating this instruction?
170 // If m_curr_insn_restored_a_register == true, we're looking at an epilogue instruction.
193 // after this instruction completes executing
[all...] |
| /external/llvm/test/MC/AArch64/ |
| arm64-diags.s | 12 ; CHECK-ERRORS: error: invalid operand for instruction
16 ; CHECK-ERRORS: error: invalid operand for instruction
45 ; CHECK-ERRORS: error: invalid operand for instruction
51 ; CHECK-ERRORS: error: invalid operand for instruction
149 ; CHECK-ERRORS: error: invalid type suffix for instruction
182 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
185 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
188 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
191 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
194 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==R
[all...] |
| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | 10 // This file contains the actual instruction interpreter.
47 // Binary Instruction Implementations
61 dbgs() << "Unhandled type for FAdd instruction: " << *Ty << "\n";
72 dbgs() << "Unhandled type for FSub instruction: " << *Ty << "\n";
83 dbgs() << "Unhandled type for FMul instruction: " << *Ty << "\n";
94 dbgs() << "Unhandled type for FDiv instruction: " << *Ty << "\n";
109 dbgs() << "Unhandled type for Rem instruction: " << *Ty << "\n";
333 dbgs() << "Unhandled type for FCmp EQ instruction: " << *Ty << "\n";
389 dbgs() << "Unhandled type for FCmp NE instruction: " << *Ty << "\n";
409 dbgs() << "Unhandled type for FCmp LE instruction: " << *Ty << "\n"
[all...] |
| /art/compiler/dex/quick/x86/ |
| fp_x86.cc | 26 void X86Mir2Lir::GenArithOpFloat(Instruction::Code opcode,
36 case Instruction::ADD_FLOAT_2ADDR:
37 case Instruction::ADD_FLOAT:
40 case Instruction::SUB_FLOAT_2ADDR:
41 case Instruction::SUB_FLOAT:
44 case Instruction::DIV_FLOAT_2ADDR:
45 case Instruction::DIV_FLOAT:
48 case Instruction::MUL_FLOAT_2ADDR:
49 case Instruction::MUL_FLOAT:
52 case Instruction::REM_FLOAT_2ADDR
[all...] |
| /art/compiler/optimizing/ |
| code_generator_arm.h | 150 void HandleFieldSet(HInstruction* instruction, const FieldInfo& field_info);
151 void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
184 HInstruction* instruction);
187 void HandleFieldSet(HInstruction* instruction, const FieldInfo& field_info);
188 void HandleFieldGet(HInstruction* instruction, const FieldInfo& field_info);
189 void GenerateImplicitNullCheck(HNullCheck* instruction);
190 void GenerateExplicitNullCheck(HNullCheck* instruction);
191 void GenerateTestAndBranch(HInstruction* instruction,
212 void Move(HInstruction* instruction, Location location, HInstruction* move_for) OVERRIDE;
273 int32_t offset, HInstruction* instruction, uint32_t dex_pc, SlowPathCode* slow_path)
[all...] |
| /art/tools/dexfuzz/src/dexfuzz/program/mutators/ |
| RandomInstructionGenerator.java | 25 import dexfuzz.rawdex.Instruction;
148 OpcodeInfo newOpcodeInfo = Instruction.getOpcodeInfo(newOpcode);
208 Opcode newOpcode = Instruction.getOpcodeInfo(mutation.newOpcode).opcode;
222 newInsn.insn = new Instruction();
223 newInsn.insn.info = Instruction.getOpcodeInfo(mutation.newOpcode);
251 // We have a branch instruction, point it at its target.
259 Log.info("Generated random instruction: " + newInsn
262 stats.incrementStat("Generated random instruction");
269 exitInsn.insn.info = Instruction.getOpcodeInfo(Opcode.MONITOR_EXIT);
274 enterInsn.insn.info = Instruction.getOpcodeInfo(Opcode.MONITOR_ENTER)
[all...] |
| /dalvik/dx/src/com/android/dx/cf/direct/ |
| CodeObserver.java | 197 * Helper to produce the first bit of output for each instruction.
199 * @param offset the offset to the start of the instruction
222 * @param offset offset to the instruction
223 * @param length instruction length
249 * @param offset offset to the instruction
250 * @param length instruction length
273 * @param offset offset to the instruction
274 * @param length instruction length
291 * @param offset offset to the instruction
292 * @param length instruction lengt
[all...] |
| /external/llvm/include/llvm/DebugInfo/DWARF/ |
| DWARFDebugLine.h | 47 // The size in bytes of the smallest target machine instruction. Statement
52 // instruction.
97 // The program-counter value corresponding to a machine instruction
102 // instruction cannot be attributed to any source line.
109 // corresponding to a machine instruction.
111 // An unsigned integer whose value encodes the applicable instruction set
112 // architecture for the current instruction.
117 // A boolean indicating that the current instruction is the beginning of a
120 // A boolean indicating that the current instruction is the
139 // guaranteed to be in the order of ascending instruction address
[all...] |
| /external/llvm/include/llvm/Transforms/Utils/ |
| SSAUpdater.h | 22 class Instruction;
138 LoadAndStorePromoter(const SmallVectorImpl<Instruction*> &Insts,
147 void run(const SmallVectorImpl<Instruction*> &Insts) const;
149 /// \brief Return true if the specified instruction is in the Inst list.
153 virtual bool isInstInList(Instruction *I,
154 const SmallVectorImpl<Instruction*> &Insts) const;
166 /// \brief Called before each instruction is deleted.
167 virtual void instructionDeleted(Instruction *I) const {
170 /// \brief Called to update debug info associated with the instruction.
171 virtual void updateDebugInfo(Instruction *I) const
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUInstrInfo.h | 1 //===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
137 /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
138 /// Return -1 if the target-specific opcode for the pseudo instruction does
139 /// not exist. If Opcode is not a pseudo instruction, this is identity.
142 /// \brief Return the descriptor of the target-specific machine instruction
168 /// \brief Build instruction(s) for an indirect register write.
170 /// \returns The instruction that performs the indirect register write
176 /// \brief Build instruction(s) for an indirect register read.
178 /// \returns The instruction that performs the indirect register read
184 /// \brief Build a MOV instruction
[all...] |
| /ndk/tests/standalone/builtin-macros/ |
| run.sh | 174 macro_check __i686__ 1 "i686 instruction set"
176 macro_check __MMX__ 1 "MMX instruction set"
177 macro_check __SSE__ 1 "SSE instruction set"
178 macro_check __SSE2__ 1 "SSE2 instruction set"
179 macro_check __SSE3__ 1 "SSE3 instruction set"
212 macro_check __MMX__ 1 "MMX instruction set"
213 macro_check __SSE__ 1 "SSE instruction set"
214 macro_check __SSE2__ 1 "SSE2 instruction set"
215 macro_check __SSE3__ 1 "SSE3 instruction set"
218 #macro_check __SSSE3__ 1 "SSSE3 instruction set
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 92 bool selectLogicalOp(const Instruction *I);
93 bool selectLoad(const Instruction *I);
94 bool selectStore(const Instruction *I);
95 bool selectBranch(const Instruction *I);
96 bool selectCmp(const Instruction *I);
97 bool selectFPExt(const Instruction *I);
98 bool selectFPTrunc(const Instruction *I);
99 bool selectFPToInt(const Instruction *I, bool IsSigned);
100 bool selectRet(const Instruction *I);
101 bool selectTrunc(const Instruction *I)
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | 119 Expression create_expression(Instruction* I);
168 Expression ValueTable::create_expression(Instruction *I) {
172 for (Instruction::op_iterator OI = I->op_begin(), OE = I->op_end();
180 assert(I->getNumOperands() == 2 && "Unsupported commutative instruction!");
205 assert((Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) &&
235 e.opcode = Instruction::Add;
239 e.opcode = Instruction::Sub;
243 e.opcode = Instruction::Mul;
262 for (Instruction::op_iterator OI = EI->op_begin(), OE = EI->op_end()
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_peephole.cpp | 34 Instruction::isNop() const
62 bool Instruction::isDead() const
95 Instruction *mov, *si, *next;
122 void checkSwapSrc01(Instruction *);
124 bool isCSpaceLoad(Instruction *);
125 bool isImmd32Load(Instruction *);
126 bool isAttribOrSharedLoad(Instruction *);
130 LoadPropagation::isCSpaceLoad(Instruction *ld)
136 LoadPropagation::isImmd32Load(Instruction *ld)
144 LoadPropagation::isAttribOrSharedLoad(Instruction *ld
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.cpp | 11 // It contains the implementation of the instruction decoder.
26 /// instruction each possible value of the ModR/M byte corresponds to. Once
27 /// this information is known, we have narrowed down to a single instruction.
33 /// Specifies which set of ModR/M->instruction tables to look at
39 /// Specifies which opcode->instruction tables to look at given
58 * contextForAttrs - Client for the instruction context table. Takes a set of
63 * an instruction with these attributes.
70 * modRMRequired - Reads the appropriate instruction table to determine whether
71 * the ModR/M byte is required to decode a particular instruction.
74 * @param insnContext - The context for the instruction, as returned b
[all...] |
