| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 160 Value *simplify(Instruction *FAdd);
167 Value *performFactorization(Instruction *I);
180 void createInstPostProc(Instruction *NewInst, bool NoNumber = false);
183 Instruction *Instr;
353 Instruction *I = nullptr;
354 if (!Val || !(I = dyn_cast<Instruction>(Val)))
359 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub) {
382 if (Opcode == Instruction::FSub)
394 if (I->getOpcode() == Instruction::FMul)
[all...] |
| /art/compiler/optimizing/ |
| ssa_liveness_analysis.cc | 107 // Each instruction gets a lifetime position, and a block gets a lifetime
113 // to differentiate between the start and end of an instruction. Adding 2 to
114 // the lifetime position for each instruction ensures the start of an
115 // instruction is different than the end of the previous instruction.
179 // that instruction is defined, and killing instructions that are being visited.
213 // Kill the instruction and shorten its interval.
227 HInstruction* instruction = environment->GetInstructionAt(i); local
228 bool should_be_live = ShouldBeLiveForEnvironment(current, instruction);
230 DCHECK(instruction->HasSsaIndex())
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| Insn.java | 27 * A register-based instruction. An instruction is the combination of
39 /** {@code null-ok;} spec for the result of this instruction, if any */
42 /** {@code non-null;} specs for all the sources of this instruction */
141 * means this instruction returns nothing.
151 * instruction, or null if no local variable assignment occurs. This
188 * Gets whether this instruction can possibly throw an exception. This
191 * @return {@code true} iff this instruction can possibly throw
199 * StdTypeList#EMPTY} if this instruction has no handlers,
200 * which can be <i>either</i> if this instruction can't possibl
[all...] |
| /dalvik/dx/src/com/android/dx/rop/code/ |
| Insn.java | 25 * A register-based instruction. An instruction is the combination of
37 /** {@code null-ok;} spec for the result of this instruction, if any */
40 /** {@code non-null;} specs for all the sources of this instruction */
139 * means this instruction returns nothing.
149 * instruction, or null if no local variable assignment occurs. This
186 * Gets whether this instruction can possibly throw an exception. This
189 * @return {@code true} iff this instruction can possibly throw
197 * StdTypeList#EMPTY} if this instruction has no handlers,
198 * which can be <i>either</i> if this instruction can't possibl
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| Insn.java | 25 * A register-based instruction. An instruction is the combination of
37 /** {@code null-ok;} spec for the result of this instruction, if any */
40 /** {@code non-null;} specs for all the sources of this instruction */
139 * means this instruction returns nothing.
149 * instruction, or null if no local variable assignment occurs. This
186 * Gets whether this instruction can possibly throw an exception. This
189 * @return {@code true} iff this instruction can possibly throw
197 * StdTypeList#EMPTY} if this instruction has no handlers,
198 * which can be <i>either</i> if this instruction can't possibl
[all...] |
| /external/v8/src/compiler/ |
| register-allocator.h | 9 #include "src/compiler/instruction.h"
35 // each instruction there are exactly two lifetime positions: the beginning and
36 // the end of the instruction. Lifetime positions for different instructions are
41 // the instruction with the given index.
49 // Returns the index of the instruction to which this lifetime position
56 // Returns true if this lifetime position corresponds to the instruction
60 // Returns the lifetime position for the start of the instruction which
67 // Returns the lifetime position for the end of the instruction which
74 // Returns the lifetime position for the beginning of the next instruction.
81 // instruction
[all...] |
| /art/tools/dexfuzz/src/dexfuzz/program/mutators/ |
| NonsenseStringPrinter.java | 24 import dexfuzz.rawdex.Instruction;
122 constStringInsn.insn = new Instruction();
123 constStringInsn.insn.info = Instruction.getOpcodeInfo(Opcode.CONST_STRING);
128 streamLoadInsn.insn = new Instruction();
129 streamLoadInsn.insn.info = Instruction.getOpcodeInfo(Opcode.SGET_OBJECT);
134 invokeInsn.insn = new Instruction();
135 invokeInsn.insn.info = Instruction.getOpcodeInfo(Opcode.INVOKE_VIRTUAL_RANGE);
|
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| BlockAddresses.java | 28 * start address, end address, and last instruction address.
35 /** {@code non-null;} array containing addresses for the final instruction
40 * final instruction) of each basic block (indexed by basic block
81 * Gets the instance for the final instruction of the given block.
91 * Gets the instance for the final instruction of the block with
102 * Gets the instance for the end (address after the final instruction)
113 * Gets the instance for the end (address after the final instruction)
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| BlockAddresses.java | 28 * start address, end address, and last instruction address.
35 /** {@code non-null;} array containing addresses for the final instruction
40 * final instruction) of each basic block (indexed by basic block
81 * Gets the instance for the final instruction of the given block.
91 * Gets the instance for the final instruction of the block with
102 * Gets the instance for the end (address after the final instruction)
113 * Gets the instance for the end (address after the final instruction)
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| BlockAddresses.java | 28 * start address, end address, and last instruction address.
35 /** {@code non-null;} array containing addresses for the final instruction
40 * final instruction) of each basic block (indexed by basic block
81 * Gets the instance for the final instruction of the given block.
91 * Gets the instance for the final instruction of the block with
102 * Gets the instance for the end (address after the final instruction)
113 * Gets the instance for the end (address after the final instruction)
|
| /external/lldb/source/Target/ |
| ThreadPlanStepInstruction.cpp | 30 // ThreadPlanStepInstruction: Step over the current instruction
41 ThreadPlan (ThreadPlan::eKindStepInstruction, "Step over single instruction", thread, stop_vote, run_vote),
67 s->Printf ("instruction step over");
69 s->Printf ("instruction step into");
73 s->Printf ("Stepping one instruction past ");
88 // Since we read the instruction we're stepping over from the thread,
218 log->Printf("Completed single instruction step plan.");
|
| /external/llvm/bindings/python/llvm/ |
| disassembler.py | 85 """Obtain the next instruction from an input source.
97 long number of bytes read. 0 if no instruction was read.
98 str representation of instruction. This will be the assembly that
99 represents the instruction.
118 long address of instruction.
119 long size of instruction, in bytes.
120 str representation of instruction.
|
| /external/llvm/include/llvm/MC/ |
| MCAsmBackend.h | 93 /// Check whether the given instruction may need relaxation.
95 /// \param Inst - The instruction to test.
99 /// associated instruction to be relaxed.
104 /// Relax the instruction in the given fragment to the next wider instruction.
106 /// \param Inst The instruction to relax, which may be the same as the
108 /// \param [out] Res On return, the relaxed instruction.
|
| MCTargetAsmParser.h | 131 /// ParseInstruction - Parse one assembly instruction.
133 /// The parser is positioned following the instruction name. The target
134 /// specific instruction parser should parse the entire instruction and
139 /// \param Name - The instruction name.
164 /// instruction as an actual MCInst and emit it to the specified MCStreamer.
186 /// checkTargetMatchPredicate - Validate the instruction match against
|
| /external/llvm/lib/Analysis/ |
| MemDepPrinter.cpp | 36 typedef PointerIntPair<const Instruction *, 2, DepType> InstTypePair;
39 typedef DenseMap<const Instruction *, DepSet> DepSetMap;
73 static InstTypePair getInstTypePair(const Instruction* inst, DepType type) {
100 Instruction *Inst = &I;
122 isa<VAArgInst>(Inst)) && "Unknown memory instruction!");
139 const Instruction *Inst = &I;
148 const Instruction *DepInst = I.first.getPointer();
|
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.h | 27 /// instruction would become an identity copy after coalescing.
51 /// copy instruction.
71 /// Set registers to match the copy instruction MI. Return
72 /// false if MI is not a coalescable copy instruction.
79 /// Return true if MI is a copy instruction that will become
86 /// Return true if the original copy instruction did not copy
95 /// the original copy instruction.
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCopyToCombine.cpp | 12 // replace them with a combine instruction.
118 // A COPY instruction can be combined if its arguments are IntRegs (32bit).
178 /// areCombinableOperations - Returns true if the two instruction can be merge
217 /// instruction from \p UseReg to \p DestReg over the instruction \p I.
256 // If I2 kills its operand and we move I2 over an instruction that also
257 // uses I2's use reg we need to modify that (first) instruction to now kill
265 // If the intervening instruction I:
282 // Update the intermediate instruction to with the kill flag.
303 // Track killed operands. If we move across an instruction that kills ou
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonBaseInfo.h | 27 /// instruction info tracks.
74 NoMemAccess = 0, // Not a memory acces instruction.
75 ByteAccess = 1, // Byte access instruction (memb).
76 HalfWordAccess = 2, // Half word access instruction (memh).
77 WordAccess = 3, // Word access instruction (memw).
78 DoubleWordAccess = 4 // Double word access instruction (memd)
94 // Only A-type instruction in first slot or nothing.
|
| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.cpp | 17 // Add I to the instruction sequences.
19 // Add an instruction seqeunce consisting of just I.
71 // instruction is an ADDiu or ORi. In that case, do not call GetInstSeqLsORi.
100 // Replace the first instruction and erase the second.
108 // The length of an instruction sequence is at most 7.
144 // Get the list of instruction sequences.
150 // Set Insts to the shortest instruction sequence.
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCTLSDynamicCall.cpp | 13 // register of the original instruction. The GETtlsADDR[32] is really
14 // a call instruction, so its target register is constrained to be GPR3.
100 // Expand into two ops built prior to the existing instruction.
105 // The ADDItls* instruction is the first instruction in the
117 // The COPY is the last instruction in the repair range.
121 // Move past the original instruction and remove it.
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.h | 11 // 64-bit X86 instruction sets. The main decode sequence for an assembly
12 // instruction in this disassembler is:
14 // 1. Read the prefix bytes and determine the attributes of the instruction.
39 // INSTRUCTIONS_SYM yields the name of the instruction and the encodings and
45 // instruction; the type indicates how to interpret the value once it has
52 // 7. As the last step, the disassembler translates the instruction information
57 // emits the instruction decode tables discussed above during compilation, and
|
| /external/llvm/lib/Transforms/ObjCARC/ |
| ObjCARCContract.cpp | 77 bool tryToPeepholeInstruction(Function &F, Instruction *Inst,
79 SmallPtrSetImpl<Instruction *> &DepInsts,
83 bool optimizeRetainCall(Function &F, Instruction *Retain);
86 contractAutorelease(Function &F, Instruction *Autorelease,
88 SmallPtrSetImpl<Instruction *> &DependingInstructions,
91 void tryToContractReleaseIntoStoreStrong(Instruction *Release,
113 bool ObjCARCContract::optimizeRetainCall(Function &F, Instruction *Retain) {
115 const Instruction *Call = CS.getInstruction();
147 Function &F, Instruction *Autorelease, ARCInstKind Class,
148 SmallPtrSetImpl<Instruction *> &DependingInstructions
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reg2Mem.cpp | 49 bool valueEscapes(const Instruction *Inst) const {
52 const Instruction *UI = cast<Instruction>(U);
79 // Find first non-alloca instruction and create insertion point. This is
92 std::list<Instruction*> WorkList;
105 for (std::list<Instruction*>::iterator ilb = WorkList.begin(),
121 for (std::list<Instruction*>::iterator ilb = WorkList.begin(),
|
| /external/llvm/lib/Transforms/Utils/ |
| SimplifyInstructions.cpp | 11 // The analysis is applied to every instruction, and if it simplifies then the
12 // instruction is replaced by the simplification. If you are looking for a pass
13 // that performs serious instruction folding, use the instcombine pass instead.
59 SmallPtrSet<const Instruction*, 8> S1, S2, *ToSimplify = &S1, *Next = &S2;
67 Instruction *I = BI++;
78 Next->insert(cast<Instruction>(U));
86 // more than one instruction, so simply incrementing the
|
| /external/llvm/test/Analysis/CostModel/X86/ |
| intrinsic-cost.ll | 4 ; If SSE4.1 roundps instruction is available it is cheap to lower, otherwise
25 ; CORE2: Cost Model: Found an estimated cost of 46 for instruction: %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load)
28 ; COREI7: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load)
53 ; CORE2: Cost Model: Found an estimated cost of 46 for instruction: %2 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %wide.load)
56 ; COREI7: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %wide.load)
81 ; CORE2: Cost Model: Found an estimated cost of 4 for instruction: %2 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %wide.load, <4 x float> %b, <4 x float> %c)
84 ; COREI7: Cost Model: Found an estimated cost of 4 for instruction: %2 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %wide.load, <4 x float> %b, <4 x float> %c)
|
