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  /art/compiler/optimizing/
instruction_simplifier.h 27 * Implements optimizations specific to each instruction.
  /art/runtime/arch/x86/
fault_handler_x86.cc 91 // Get the size of an instruction in bytes.
92 // Return 0 if the instruction is not handled.
208 VLOG(signals) << "Unhandled x86 instruction with opcode " << static_cast<int>(opcode);
232 VLOG(signals) << "x86 instruction length calculated as " << (pc - startpc);
288 // Unknown instruction, tell caller it's not ours.
302 // Unknown instruction, can't really happen.
308 // next instruction (this instruction + instruction size). The return address
322 // A suspend check is done using the following instruction sequence
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  /art/runtime/
dex_instruction.cc 30 const char* const Instruction::kInstructionNames[] = {
38 Instruction::Format const Instruction::kInstructionFormats[] = {
46 int const Instruction::kInstructionFlags[] = {
54 int const Instruction::kInstructionVerifyFlags[] = {
62 int const Instruction::kInstructionSizeInCodeUnits[] = {
75 int32_t Instruction::GetTargetOffset() const {
84 default: LOG(FATAL) << "Tried to access the branch offset of an instruction " << Name() <<
90 bool Instruction::CanFlowThrough() const {
94 return FlagsOf(opcode) & Instruction::kContinue
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  /art/test/800-smali/smali/
b_20843113.smali 9 # An instruction that may throw, so as to pass UninitializedThis to the handler
  /art/tools/dexfuzz/src/dexfuzz/program/mutators/
InstructionDeleter.java 77 // Pick an instruction at random...
97 stats.incrementStat("Deleted instruction");
99 // Delete the instruction.
105 // Get the data instruction.
  /cts/tools/vm-tests-tf/src/dot/junit/opcodes/move_result_object/
Test_move_result_object.java 81 * @title move-result-object instruction must be immediately preceded
82 * (in the insns array) by an <invoke-kind> instruction
90 * @title move-result-object instruction must be immediately preceded
91 * (in actual control flow) by an <invoke-kind> instruction
  /cts/tools/vm-tests-tf/src/dot/junit/opcodes/new_instance/
Test_new_instance.java 121 * @title A register which holds the result of a new-instance instruction must not be used
122 * if the same new-instance instruction is again executed before the instance is initialized
130 * @title A register which holds the result of a new-instance instruction must not be used
131 * if the same new-instance instruction is again executed before the instance is initialized
  /dalvik/dexgen/src/com/android/dexgen/dex/code/
Dop.java 29 /** {@code non-null;} the instruction format */
44 * @param format {@code non-null;} the instruction format
100 * Gets the instruction format.
102 * @return {@code non-null;} the instruction format
HighRegisterPrefix.java 26 * Combination instruction which turns into a variable number of
29 * in translating an instruction whose register requirements cannot
135 * Returns the proper move instruction for the given source spec
140 * @return {@code non-null;} the appropriate move instruction
  /dalvik/dx/src/com/android/dx/dex/code/
HighRegisterPrefix.java 25 * Combination instruction which turns into a variable number of
28 * in translating an instruction whose register requirements cannot
134 * Returns the proper move instruction for the given source spec
139 * @return {@code non-null;} the appropriate move instruction
  /dalvik/dx/src/com/android/dx/merge/
InstructionTransformer.java 52 for (DecodedInstruction instruction : mappedInstructions) {
53 if (instruction != null) {
54 instruction.encode(out);
110 " into a non-jumbo instruction!");
  /external/clang/test/CodeGen/
branch-target-layout.c 10 // order of a branch instruction's labels cannot be used as a source order bias.
linetable-endscope.c 3 // Check the line numbers for the ret instruction. We expect it to be
  /external/dexmaker/src/dx/java/com/android/dx/dex/code/
HighRegisterPrefix.java 26 * Combination instruction which turns into a variable number of
29 * in translating an instruction whose register requirements cannot
135 * Returns the proper move instruction for the given source spec
140 * @return {@code non-null;} the appropriate move instruction
  /external/kernel-headers/original/uapi/asm-mips/asm/
sgidefs.h 24 * With the introduction of MIPS32 / MIPS64 instruction sets definitions
  /external/lldb/source/Plugins/Instruction/ARM/
Makefile 1 ##===- source/Plugins/Instruction/ARM/Makefile -------------*- Makefile -*-===##
  /external/llvm/examples/ModuleMaker/
ModuleMaker.cpp 48 // Create the add instruction... does not insert...
49 Instruction *Add = BinaryOperator::Create(Instruction::Add, Two, Three,
55 // Create the return instruction and add it to the basic block
  /external/llvm/lib/Analysis/
InstCount.cpp 34 #include "llvm/IR/Instruction.def"
47 #include "llvm/IR/Instruction.def"
49 void visitInstruction(Instruction &I) {
50 errs() << "Instruction Count does not know about " << I;
  /external/llvm/lib/CodeGen/
MachineCombiner.cpp 116 /// of defining machine instruction in \p InsInstrs
119 /// \returns Depth of last instruction in \InsInstrs ("NewRoot")
128 // For each instruction in the new sequence compute the depth based on the
172 /// Computes instruction latency as max of latency of defined operands.
174 /// \param Root is a machine instruction that could be replaced by NewRoot.
176 /// case there is a dependent instruction in the same trace (\p BlockTrace)
177 /// \param NewRoot is the instruction for which the latency is computed
196 // Get the first instruction that uses MO
213 /// True when the new instruction sequence does not
215 /// (Machine Instruction) Root. The new code sequence ends in MI NewRoot.
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WinEHPrepare.cpp 114 // the landing pad instruction in the parent function from which they
158 bool isLandingPadSpecificInst(const Instruction *Inst) const;
181 const Instruction *Inst,
185 const Instruction *Inst,
188 const Instruction *Inst,
191 const Instruction *Inst,
223 const Instruction *Inst,
225 CloningAction handleEndCatch(ValueToValueMapTy &VMap, const Instruction *Inst,
228 const Instruction *Inst,
259 const Instruction *Inst
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  /external/llvm/lib/IR/
CMakeLists.txt 26 Instruction.cpp
  /external/llvm/lib/MC/
MCCodeEmitter.cpp 1 //===-- MCCodeEmitter.cpp - Instruction Encoding --------------------------===//
  /external/llvm/lib/Target/ARM/
ARMOptimizeBarriersPass.cpp 39 // Returns whether the instruction can safely move past a DMB instruction
60 // Will be true when we have seen a DMB, and not seen any instruction since
81 // If we find an instruction unable to pass past a DMB, a next DMB is
  /external/llvm/lib/Target/PowerPC/
PPCLoopPreIncPrep.cpp 172 typedef std::multimap<const SCEV *, Instruction *, SCEVLess> Bucket;
179 Instruction *MemI;
265 Instruction *MemI = Buckets[i].begin()->second;
305 Instruction *InsPoint = Header->getFirstInsertionPt();
318 Instruction *NewBasePtr;
325 if (Instruction *IDel = dyn_cast<Instruction>(BasePtr))
338 Instruction *RealNewPtr;
344 Instruction *PtrIP = dyn_cast<Instruction>(Ptr)
    [all...]
  /external/llvm/lib/Transforms/ObjCARC/
ARCInstKind.h 1 //===--- ARCInstKind.h - ARC instruction equivalence classes -*- C++ -*----===//
88 /// Test whether the given instruction can autorelease any pointer or cause an
96 /// \brief Determine which objc runtime call instruction class V belongs to.
116 /// Returns false if conservatively we can prove that any instruction mapped to

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