| /external/llvm/lib/Target/Mips/ |
| MipsInstrFPU.td | 371 def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
373 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| select.ll | 247 ; CMOV-32R2-R5: mthc1 $6, $[[F0]]
253 ; SEL-32: mthc1 $6, $[[F0]]
|
| /external/v8/src/mips/ |
| disasm-mips.cc | 475 case MTHC1:
476 Format(instr, "mthc1 'rt, 'fs");
[all...] |
| macro-assembler-mips.h | 250 Mthc1(src_high, dst);
758 void Mthc1(Register rt, FPURegister fs);
[all...] |
| /external/v8/src/mips64/ |
| disasm-mips64.cc | 503 case MTHC1:
504 Format(instr, "mthc1 'rt, 'fs");
[all...] |
| /external/v8/test/cctest/ |
| test-assembler-mips.cc | 372 __ mthc1(t1, f6);
374 __ mthc1(t3, f4);
[all...] |
| test-assembler-mips64.cc | 377 __ mthc1(a5, f5);
816 __ mthc1(a5, f8); // f8 MS 32-bits.
[all...] |
| /art/compiler/dex/quick/mips/ |
| int_mips.cc | 237 // note the operands are swapped for the mtc1 and mthc1 instr.
|
| /art/disassembler/ |
| disassembler_mips.cc | 291 { kFpMask | (0x1f << 21), kCop1 | (0x07 << 21), "mthc1", "Td" },
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| valid-mips32r2-le.txt | 116 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
|
| valid-mips32r2.txt | 116 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| valid-mips32r3-le.txt | 113 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
|
| valid-mips32r3.txt | 113 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| valid-mips32r5-le.txt | 113 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
|
| valid-mips32r5.txt | 113 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| valid-mips64r2-el.txt | 175 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
|
| valid-mips64r2.txt | 175 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| valid-mips64r3-el.txt | 172 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
|
| valid-mips64r3.txt | 172 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| valid-mips64r5-el.txt | 172 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
|
| valid-mips64r5.txt | 172 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 134 mthc1 $zero,$f16
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 134 mthc1 $zero,$f16
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 134 mthc1 $zero,$f16
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 198 mthc1 $zero,$f16
|
