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  /external/llvm/test/CodeGen/SystemZ/
frame-01.ll 23 ; two emergency spill slots at 160(%r15), for instructions with unsigned
frame-14.ll 24 ; emergency spill slots at 160(%r15), the amount that we need to allocate
229 ; Repeat f4 in a case that needs the emergency spill slots (because all
267 ; And again with maximum register pressure. The only spill slots that the
269 ; The FP case needs to spill an extra register and is too dependent on
frame-16.ll 24 ; emergency spill slots at 160(%r15), the amount that we need to allocate
219 ; Repeat f4 in a case that needs the emergency spill slots (because all
253 ; And again with maximum register pressure. The only spill slots that the
256 ; spill a second register. This leads to an extra displacement of 8.
frame-08.ll 6 ; It is big enough to require two emergency spill slots at 160(%r15),
74 ; It is big enough to require two emergency spill slots at 160(%r15),
  /external/llvm/test/CodeGen/XCore/
exception.ll 53 ; N.B. we alloc no variables, hence force compiler to spill
  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_wm_debug.c 92 printf("/SPILL(%x)",inst->dst[i]->spill_slot);
  /external/v8/src/compiler/
linkage.cc 69 // Local or spill slot. Skip the frame pointer, function, and
  /packages/apps/FMRadio/res/values-nb/
strings.xml 43 <string name="fm_turn_on" msgid="407678074231499621">"Spill av og stopp FM-radio"</string>
  /packages/apps/Settings/res/values-nb/
arrays.xml 291 <item msgid="1097324338692486211">"spill inn lyd"</item>
292 <item msgid="5031552983987798163">"spill av lyd"</item>
343 <item msgid="1720492593061838172">"Spill inn lyd"</item>
344 <item msgid="3493046322001257041">"Spill av lyd"</item>
  /art/compiler/utils/x86_64/
assembler_x86_64_test.cc     [all...]
  /external/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 524 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
528 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
565 // spill + reload via ldc1
575 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
579 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
  /art/compiler/dex/quick/arm64/
codegen_arm64.h 360 // Spill core and FP registers. Returns the SP difference: either spill size, or whole
  /art/compiler/dex/quick/mips/
call_mips.cc 310 // Spill core callee saves.
312 // NOTE: promotion of FP regs currently unsupported, thus no FP spill.
  /art/compiler/dex/quick/x86/
call_x86.cc 190 /* Spill core callee saves */
218 // spill ebp
  /art/compiler/optimizing/
code_generator.h 255 // Clears the spill slots taken by loop phis in the `LocationSummary` of the
258 // is, which is the loop entry). At this point, the spill slots for the phis
code_generator_x86.h 216 // 8 bytes == 2 words for each spill.
  /bionic/libc/arch-arm/generic/bionic/
memcpy.S 100 /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
214 /* Use post-increment mode for stm to spill r5-r11 to reserved stack
  /bionic/libc/arch-mips/bionic/
setjmp.S 196 REG_S ra, RAOFF(sp) # spill state
298 REG_S a1, A1OFF(sp) # temp spill
  /external/llvm/lib/Target/ARM/
README-Thumb.txt 18 temporaries to spill values into.
186 These instructions preserve the condition code which is important if the spill
ARMMachineFunctionInfo.h 67 /// spill stack offset.
  /external/llvm/test/CodeGen/ARM/
struct-byval-frame-index.ll 3 ; Check a spill right after a function call with large struct byval is correctly
8 ; CHECK: str r{{.*}}, [sp, [[SLOT:#[0-9]+]]] @ 4-byte Spill
  /external/llvm/test/CodeGen/X86/
movtopush.ll 250 ; Make sure we reference the correct stack slot - we spill into (%esp)
255 ; NORMAL-NEXT: movl [[EAX]], (%esp) # 4-byte Spill
pr18846.ll 6 ; pr18846 - needless avx spill/reload
12 ;CHECK-NOT: vmovups {{.*#+}} 32-byte Folded Spill
  /external/valgrind/coregrind/
pub_core_threadstate.h 94 guest state area, its two shadows, and the spill area, are
108 /* Spill area. */
  /external/llvm/include/llvm/CodeGen/PBQP/
ReductionRules.h 153 // An empty or spill only cost vector does not provide any register option.

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