| /art/compiler/utils/arm/ |
| assembler_arm.cc | 423 ManagedRegisterSpill spill = entry_spills.at(i);
424 offset += spill.getSize();
[all...] |
| /external/libunwind/src/ia64/ |
| Gparser.c | 196 Dprintf ("libunwind: excess spill!\n");
247 /* Next, lay out the memory stack spill area. */
|
| Gregs.c | 211 the UNaT slot number (as determined by st8.spill) and the
|
| /external/llvm/lib/CodeGen/ |
| StackColoring.cpp | 14 // NOTE: This pass is not StackSlotColoring, which optimizes spill slots.
20 // spill slots.
|
| TargetInstrInfo.cpp | 422 // Compute the spill slot size and offset.
428 report_fatal_error("cannot spill patchpoint subregister operand");
[all...] |
| MachineFunction.cpp | 523 /// represents a spill slot, returning a nonnegative identifier to represent
572 /// CreateFixedSpillStackObject - Create a spill slot at a fixed location
[all...] |
| StackMaps.cpp | 126 // The stack map also records the size of a spill slot that can hold the
|
| /external/llvm/test/CodeGen/X86/ |
| stack-folding-int-avx1.ll | 8 ; By including a nop call with sideeffects we can force a partial register spill of the
77 ;CHECK: movd {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 4-byte Folded Spill
97 ;CHECK: movq {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 8-byte Folded Spill
431 ;CHECK: pextrd $1, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 4-byte Folded Spill
440 ;CHECK: pextrq $1, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 8-byte Folded Spill
[all...] |
| stack-folding-int-sse42.ll | 8 ; By including a nop call with sideeffects we can force a partial register spill of the
104 ;CHECK: movd {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 4-byte Folded Spill
124 ;CHECK: movq {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 8-byte Folded Spill
458 ;CHECK: pextrd $1, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 4-byte Folded Spill
467 ;CHECK: pextrq $1, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 8-byte Folded Spill
[all...] |
| /art/compiler/dex/quick/x86/ |
| x86_lir.h | 88 * | spill region | {variable sized}
164 // fake return address register for core spill mask.
[all...] |
| target_x86.cc | 88 // 4.3) Update jni_entrypoints to spill/unspill new callee save reg
89 // 4.4) Update quick_entrypoints to spill/unspill new callee save reg
739 // Spill mask not including fake return address register
760 // Spill mask not including fake return address register
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.cc | 1097 ManagedRegisterSpill spill = entry_spills.at(i); local
1098 int32_t size = spill.getSize();
[all...] |
| /art/runtime/arch/arm/ |
| quick_entrypoints_arm.S | 387 push {r4, r5, r6, r7, r8, r9, r10, r11, lr} @ spill regs
439 pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} @ restore spill regs
[all...] |
| /external/v8/src/compiler/ia32/ |
| code-generator-ia32.cc | 47 // The linkage computes where all spill slots are located.
762 // Remove this frame's spill slots first.
[all...] |
| /frameworks/base/packages/SystemUI/res/values-nb/ |
| strings.xml | [all...] |
| /art/compiler/dex/quick/ |
| mir_to_lir.h | 629 * @return Returns the size in bytes for space needed for compiler temporary spill region.
[all...] |
| /external/jmonkeyengine/engine/src/core-plugins/com/jme3/texture/plugins/ |
| TGALoader.java | 476 // start at data[offsetBytes]... spill into next byte as needed.
|
| /external/libogg/src/ |
| framing.c | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| Passes.h | 425 /// SpillPlacement analysis. Suggest optimal placement of spill code between
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | 613 // We assume a single instruction only has a spill or reload, not
627 CommentOS << MMO->getSize() << "-byte Spill\n";
631 CommentOS << MMO->getSize() << "-byte Folded Spill\n";
634 // Check for spill-induced copies
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 21 // spill placement, only here we're determining where to place cross-class
|
| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.td | 197 // know how to spill them. If we make our prologue/epilogue code smarter at
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 12 // allocation, but because we have a spill in between the feeder and new value
|
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.cpp | 178 // It's killed at the spill, unless the register is RA and return address
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 444 // We don't want to spill/restore the counter register, and so we don't
|
