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  /external/llvm/test/TableGen/
TargetInstrSpec.td 4 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
5 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
7 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
8 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
86 def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
87 !strconcat(asmstr, "\t$dst, $src1, $src2"),
93 def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
94 !strconcat(asmstr, "\t$dst, $src1, $src2"),
102 [(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))]>;
MultiPat.td 107 def PS : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
108 !strconcat(asmstr, "\t$dst, $src1, $src2"), !cast<Intrinsic>(!subst("SUFFIX", "_ps", intr)), patterns>;
110 def PD : Base<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
111 !strconcat(asmstr, "\t$dst, $src1, $src2"), !cast<Intrinsic>(!subst("SUFFIX", "_pd", intr)), patterns>;
116 [[(set REGCLASS:$dst, (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))],
117 [(set REGCLASS:$dst, (bitconvert (INTRINSIC REGCLASS:$src1, REGCLASS:$src2))),
120 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
121 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
usevalname.td 20 RC:$src1, RC:$src2))]>;
  /external/vixl/src/vixl/a64/
logic-a64.cc 703 const LogicVRegister& src2,
708 int64_t sb = src2.Int(vform, i);
710 uint64_t ub = src2.Uint(vform, i);
742 const LogicVRegister& src2) {
746 uint64_t ub = src2.Uint(vform, i);
756 const LogicVRegister& src2) {
762 uint64_t ub = src2.UintLeftJustified(vform, i);
770 int64_t sb = src2.IntLeftJustified(vform, i);
778 dst.SetInt(vform, i, src1.Int(vform, i) + src2.Int(vform, i));
787 const LogicVRegister& src2) {
3308 add(VectorFormatDoubleWidth(vform), temp, src1, src2); local
3330 add(VectorFormatDoubleWidth(vform), temp, src1, src2); local
3352 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); local
3374 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); local
    [all...]
  /external/bison/lib/
vbitset.c 502 vbitset_and (bitset dst, bitset src1, bitset src2)
512 vbitset_resize (dst, max (BITSET_SIZE_ (src1), BITSET_SIZE_ (src2)));
516 ssize2 = VBITSET_SIZE (src2);
519 src2p = VBITSET_WORDS (src2);
529 vbitset_and_cmp (bitset dst, bitset src1, bitset src2)
540 vbitset_resize (dst, max (BITSET_SIZE_ (src1), BITSET_SIZE_ (src2)));
544 ssize2 = VBITSET_SIZE (src2);
547 src2p = VBITSET_WORDS (src2);
582 vbitset_andn (bitset dst, bitset src1, bitset src2)
592 vbitset_resize (dst, max (BITSET_SIZE_ (src1), BITSET_SIZE_ (src2)));
    [all...]
  /external/opencv/cxcore/src/
cxarithm.cpp 60 worktype t0 = __op__((src1)[i], (src2)[i]); \
61 worktype t1 = __op__((src1)[i+1], (src2)[i+1]); \
66 t0 = __op__((src1)[i+2],(src2)[i+2]); \
67 t1 = __op__((src1)[i+3],(src2)[i+3]); \
75 worktype t0 = __op__((src1)[i],(src2)[i]); \
82 ( const type* src1, int step1, const type* src2, int step2, \
84 (src1, step1, src2, step2, dst, step, size) ) \
86 step1/=sizeof(src1[0]); step2/=sizeof(src2[0]); step/=sizeof(dst[0]); \
90 for( ; size.height--; src1 += step1, src2 += step2, dst += step ) \
92 worktype t0 = __op__((src1)[0],(src2)[0]);
286 CvMat srcstub1, srcstub2, *src1, *src2; local
762 CvMat srcstub2, *src2 = (CvMat*)srcarr2; local
1322 CvMat srcstub2, *src2 = (CvMat*)srcarr2; local
1670 CvMat srcstub2, *src2 = (CvMat*)srcarr2; local
    [all...]
cxlogic.cpp 63 ( const uchar* src1, int step1, const uchar* src2, int step2, \
64 uchar* dst, int step, CvSize size ), (src1, step1, src2, step2, dst, step, size) )\
66 for( ; size.height--; src1 += step1, src2 += step2, dst += step ) \
70 if( (((size_t)src1 | (size_t)src2 | (size_t)dst) & 3) == 0 ) \
74 int t0 = __op__(((const int*)(src1+i))[0], ((const int*)(src2+i))[0]);\
75 int t1 = __op__(((const int*)(src1+i))[1], ((const int*)(src2+i))[1]);\
80 t0 = __op__(((const int*)(src1+i))[2], ((const int*)(src2+i))[2]); \
81 t1 = __op__(((const int*)(src1+i))[3], ((const int*)(src2+i))[3]); \
89 int t = __op__(*(const int*)(src1+i), *(const int*)(src2+i)); \
96 int t = __op__(((const uchar*)src1)[i],((const uchar*)src2)[i]);
353 CvMat srcstub2, *src2 = (CvMat*)srcarr2; local
    [all...]
cxcmp.cpp 58 a2 = src2[x], a3 = src3[x]; \
68 a2 = src2[x*2], a3 = src3[x*2]; \
71 a2 = src2[x*2+1]; \
82 a2 = src2[x*3], a3 = src3[x*3]; \
85 a2 = src2[x*3+1]; \
89 a2 = src2[x*3+2]; \
100 a2 = src2[x*4], a3 = src3[x*4]; \
103 a2 = src2[x*4+1]; \
107 a2 = src2[x*4+2]; \
111 a2 = src2[x*4+3];
257 CvMat srcstub2, *src2 = (CvMat*)srcarr2; local
568 CvMat srcstub2, *src2 = (CvMat*)srcarr2; local
976 CvMat srcstub2, *src2 = (CvMat*)srcarr2; local
1426 CvMat srcstub2, *src2 = (CvMat*)srcarr2; local
    [all...]
  /external/llvm/lib/ExecutionEngine/Interpreter/
Execution.cpp 52 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
56 GenericValue Src2, Type *Ty) {
67 GenericValue Src2, Type *Ty) {
78 GenericValue Src2, Type *Ty) {
89 GenericValue Src2, Type *Ty) {
100 GenericValue Src2, Type *Ty) {
103 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal);
106 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal);
116 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
121 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size());
    [all...]
  /external/llvm/test/CodeGen/AArch64/
arm64-sli-sri-opt.ll 3 define void @testLeftGood(<16 x i8> %src1, <16 x i8> %src2, <16 x i8>* %dest) nounwind {
7 %vshl_n = shl <16 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
13 define void @testLeftBad(<16 x i8> %src1, <16 x i8> %src2, <16 x i8>* %dest) nounwind {
17 %vshl_n = shl <16 x i8> %src2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
23 define void @testRightGood(<16 x i8> %src1, <16 x i8> %src2, <16 x i8>* %dest) nounwind {
27 %vshl_n = lshr <16 x i8> %src2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
33 define void @testRightBad(<16 x i8> %src1, <16 x i8> %src2, <16 x i8>* %dest) nounwind {
37 %vshl_n = lshr <16 x i8> %src2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
  /external/llvm/test/CodeGen/R600/
llvm.AMDGPU.umad24.ll 15 define void @test_umad24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
16 %mad = call i32 @llvm.AMDGPU.umad24(i32 %src0, i32 %src1, i32 %src2) nounwind readnone
23 ; SI-DAG: buffer_load_dword [[SRC2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
24 ; SI: v_mad_u32_u24 [[RESULT:v[0-9]+]], 4, [[SRC0]], [[SRC2]]
30 %src2.gep = getelementptr i32, i32 addrspace(1)* %src0.gep, i32 1
33 %src2 = load i32, i32 addrspace(1)* %src2.gep, align 4
34 %mad = call i32 @llvm.AMDGPU.umad24(i32 %src0, i32 4, i32 %src2) nounwind readnone
llvm.amdgpu.lrp.ll 9 define void @test_lrp(float addrspace(1)* %out, float %src0, float %src1, float %src2) nounwind {
10 %mad = call float @llvm.AMDGPU.lrp(float %src0, float %src1, float %src2) nounwind readnone
llvm.AMDGPU.bfi.ll 10 define void @bfi_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
28 define void @bfi_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind {
29 %bfi = call i32 @llvm.AMDGPU.bfi(i32 %src0, i32 123, i32 %src2) nounwind readnone
37 define void @bfi_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind {
38 %bfi = call i32 @llvm.AMDGPU.bfi(i32 123, i32 %src1, i32 %src2) nounwind readnone
  /external/vboot_reference/firmware/stub/
utility_stub.c 20 int Memcmp(const void *src1, const void *src2, size_t n)
22 return memcmp(src1, src2, n);
  /prebuilts/ndk/4/platforms/android-5/arch-x86/usr/include/asm/
mpspec_32.h 33 #define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
34 #define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
  /prebuilts/ndk/4/platforms/android-8/arch-x86/usr/include/asm/
mpspec_32.h 33 #define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
34 #define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
  /prebuilts/ndk/6/platforms/android-9/arch-x86/usr/include/asm/
mpspec_32.h 33 #define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
34 #define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
  /prebuilts/ndk/7/platforms/android-14/arch-x86/usr/include/asm/
mpspec_32.h 33 #define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
34 #define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
  /prebuilts/ndk/7/platforms/android-9/arch-x86/usr/include/asm/
mpspec_32.h 33 #define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
34 #define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
  /system/core/libutils/tests/
String8_test.cpp 62 String8 src2(" is my passport.");
63 src1 += src2;
65 EXPECT_STREQ(src2.string(), " is my passport.");
71 EXPECT_STREQ(src2.string(), " is my passport.");
  /external/llvm/lib/Target/X86/
X86InstrVMX.td 19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
20 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
23 "invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
26 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
27 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
29 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/radeon/
radeon_tile.c 53 uint8_t *src2 = (uint8_t *)src + src_pitch * row + col; local
61 memcpy(dst2, src2, columns * sizeof(uint8_t));
63 src2 += src_pitch;
84 uint16_t *src2 = (uint16_t *)src + src_pitch * row + col; local
92 memcpy(dst2, src2, columns * sizeof(uint16_t));
94 src2 += src_pitch;
115 uint16_t *src2 = (uint16_t *)src + src_pitch * row + col; local
123 memcpy(dst2, src2, columns * sizeof(uint16_t));
125 src2 += src_pitch;
146 uint32_t *src2 = (uint32_t *)src + src_pitch * row + col local
177 uint64_t *src2 = (uint64_t *)src + src_pitch * row + col; local
269 uint8_t *src2 = (uint8_t *)src + row * src_pitch + local
302 uint16_t *src2 = (uint16_t *)src + row * src_pitch + local
335 uint16_t *src2 = (uint16_t *)src + row * src_pitch + local
368 uint32_t *src2 = (uint32_t *)src + row * src_pitch + local
401 uint64_t *src2 = (uint64_t *)src + row * src_pitch + local
    [all...]
  /external/opencv/cv/src/
cvderiv.cpp 90 float* src2 = src + src_step; local
94 buffer[x] = (float)(ky[0]*src[x] + ky[1]*src2[x] + ky[2]*src3[x]);
575 const int *src0 = src[-1], *src1 = src[0], *src2 = src[1]; local
580 int s0 = src0[i] - src1[i]*2 + src2[i] + src1[i+width];
581 int s1 = src0[i+1] - src1[i+1]*2 + src2[i+1] + src1[i+width+1];
586 dst[i] = (short)(src0[i] - src1[i]*2 + src2[i] + src1[i+width]);
591 int s0 = src0[i] - src1[i]*2 + src2[i] +
592 src0[i+width] + src1[i+width]*2 + src2[i+width];
593 int s1 = src0[i+1] - src1[i+1]*2 + src2[i+1] +
594 src0[i+width+1] + src1[i+width+1]*2 + src2[i+width+1]
609 const int *src0 = src[-2], *src1 = src[-1], *src2 = src[0], *src3 = src[1], *src4 = src[2]; local
643 const int* src1 = src[k] + i, *src2 = src[-k] + i; local
659 const int* src1 = src[k] + i, *src2 = src[-k] + i; local
675 const int* src1 = src[k] + i, *src2 = src[-k] + i; local
717 const float *src0 = src[-1], *src1 = src[0], *src2 = src[1]; local
751 const float *src0 = src[-2], *src1 = src[-1], *src2 = src[0], *src3 = src[1], *src4 = src[2]; local
772 const float* src1 = src[k] + i, *src2 = src[-k] + i; local
788 const float* src1 = src[k] + i, *src2 = src[-k] + i; local
    [all...]
  /external/libvpx/libvpx/vp8/common/x86/
mfqe_sse2.asm 163 ; unsigned char *src2, 2
180 mov rdx, arg(2) ; src2
187 pxor xmm4, xmm4 ; sum of src2
188 pxor xmm5, xmm5 ; sum of src2^2
194 movdqa xmm1, [rdx] ; src2
196 add rdx, rdi ; src2 + stride2
198 ; SAD(src1, src2)
202 ; SUM(src2)
204 psadbw xmm2, xmm1 ; sum src2 by misusing SAD against 0
233 ; Accumulate sum of src2
    [all...]
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/x86/
mfqe_sse2.asm 163 ; unsigned char *src2, 2
180 mov rdx, arg(2) ; src2
187 pxor xmm4, xmm4 ; sum of src2
188 pxor xmm5, xmm5 ; sum of src2^2
194 movdqa xmm1, [rdx] ; src2
196 add rdx, rdi ; src2 + stride2
198 ; SAD(src1, src2)
202 ; SUM(src2)
204 psadbw xmm2, xmm1 ; sum src2 by misusing SAD against 0
233 ; Accumulate sum of src2
    [all...]

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