| /external/llvm/test/CodeGen/R600/ |
| mad_int24.ll | 30 define void @test_imul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
32 %add = add i32 %mul, %src2
|
| /frameworks/av/media/libeffects/lvm/lib/Common/lib/ |
| Mixer.h | 82 const LVM_INT32 *src2,
102 const LVM_INT32 *src2,
|
| /frameworks/av/media/libeffects/lvm/lib/Common/src/ |
| LVC_Mixer.h | 113 LVM_INT16 *src2,
114 LVM_INT16 *dst, /* dst cannot be equal to src2 */
|
| LVC_Mixer_Private.h | 66 const LVM_INT16 *src2,
112 const LVM_INT32 *src2,
|
| /system/vold/tests/ |
| VolumeManager_test.cpp | 56 const char* src2 = "android"; local
58 EXPECT_FALSE(VolumeManager::asecHash(src2, dst, sizeof(buffer)) == NULL)
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.td | 476 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
477 "crc32 $dst, $src2, $src3",
479 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
519 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
520 "ladd $dst2, $dst1, $src1, $src2, $src3",
524 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
525 "lsub $dst2, $dst1, $src1, $src2, $src3", []>;
528 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
529 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
535 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4)
[all...] |
| /external/apache-harmony/beans/src/test/java/org/apache/harmony/beans/tests/java/beans/ |
| PropertyChangeSupportTest.java | 794 Object src2 = new Object() local
826 Object src2 = new Object(); local
858 Object src2 = new Object(); local
890 Object src2 = new Object(); local
922 Object src2 = new Object(); local
953 Object src2 = new Object(); local
[all...] |
| /art/test/003-omnibus-opcodes/ |
| build | 23 ${JAVAC} -d classes `find src2 -name '*.java'`
|
| /external/llvm/lib/Target/R600/ |
| VIInstrFormats.td | 114 bits<9> src2;
127 let Inst{58-50} = src2;
141 bits<9> src2;
153 let Inst{58-50} = src2;
|
| /external/llvm/test/CodeGen/ARM/ |
| pack.ll | 95 define i32 @test9(i32 %src1, i32 %src2) {
98 %tmp2 = lshr i32 %src2, 16
105 define i32 @test10(i32 %src1, i32 %src2) {
108 %tmp2 = ashr i32 %src2, 17
|
| /external/pcre/dist/sljit/ |
| sljitLir.c | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.td | 70 (ins IntRegs:$src1, ImmOp:$src2),
71 "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)",
75 bits<10> src2;
84 let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9});
86 let Inst{13-5} = src2{8-0};
97 : Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
98 (MI IntRegs:$src1, ImmPred:$src2)>;
508 (ins PredRegs:$src1, IntRegs:$src2),
511 ") $dst = $src2"> {
514 bits<5> src2;
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_opcodes.h | 53 /** vec4 instruction: dst.c = clamp(src0.c, src1.c, src2.c) */
56 /** vec4 instruction: dst.c = src0.c < 0.0 ? src1.c : src2.c */
59 /** vec4 instruction: dst.c = src2.c > 0.5 ? src0.c : src1.c */
112 /** vec4 instruction: dst.c = src0.c*src1.c + (1 - src0.c)*src2.c */
115 /** vec4 instruction: dst.c = src0.c*src1.c + src2.c */
|
| /external/opencv/cxcore/include/ |
| cxcore.h | 461 const CvArr* src2, const CvArr* src3,
506 /* dst(mask) = src1(mask) + src2(mask) */
507 CVAPI(void) cvAdd( const CvArr* src1, const CvArr* src2, CvArr* dst,
514 /* dst(mask) = src1(mask) - src2(mask) */
515 CVAPI(void) cvSub( const CvArr* src1, const CvArr* src2, CvArr* dst,
530 /* dst(idx) = src1(idx) * src2(idx) * scale
532 CVAPI(void) cvMul( const CvArr* src1, const CvArr* src2,
536 dst(idx) = src1(idx) * scale / src2(idx)
537 or dst(idx) = scale / src2(idx) if src1 == 0 */
538 CVAPI(void) cvDiv( const CvArr* src1, const CvArr* src2,
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZSelectionDAGInfo.cpp | 156 // Use CLC to compare [Src1, Src1 + Size) with [Src2, Src2 + Size),
159 SDValue Src1, SDValue Src2, uint64_t Size) {
171 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2,
174 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2,
193 SDValue Src1, SDValue Src2, SDValue Size,
199 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes);
246 SDValue Src1, SDValue Src2,
250 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2,
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc_emit.c | 116 uint saturate, uint src0, uint src1, uint src2)
129 if (GET_UREG_TYPE(src2) == REG_TYPE_CONST)
142 s[2] = src2;
158 src2 = s[2];
165 *(p->csr++) = (A2_SRC1(src1) | A2_SRC2(src2));
228 coord, 0, 0 ); /* src0, src1, src2 */
|
| /external/v8/src/mips/ |
| lithium-codegen-mips.h | 234 const Operand& src2 = Operand(zero_reg),
238 const Operand& src2 = Operand(zero_reg),
283 const Operand& src2);
288 FPURegister src2);
293 const Operand& src2);
298 FPURegister src2);
|
| /external/v8/src/mips64/ |
| lithium-codegen-mips64.h | 235 const Operand& src2 = Operand(zero_reg),
239 const Operand& src2 = Operand(zero_reg),
284 const Operand& src2);
289 FPURegister src2);
294 const Operand& src2);
299 FPURegister src2);
|
| /external/llvm/docs/TableGen/ |
| index.rst | 99 dag InOperandList = (ins GR32:$src1, GR32:$src2);
100 string AsmString = "add{l}\t{$src2, $dst|$dst, $src2}";
101 list<dag> Pattern = [(set GR32:$dst, (add GR32:$src1, GR32:$src2))];
164 (ins GR32:$src1, GR32:$src2),
165 "add{l}\t{$src2, $dst|$dst, $src2}",
166 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
|
| /external/llvm/lib/Target/X86/ |
| README-FPStack.txt | 18 def FpADD32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
20 (extloadf64f32 addr:$src2)))]>;
23 def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
25 (X86fild addr:$src2, i32)))]>;
|
| X86InstrFragmentsSIMD.td | 632 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
633 (masked_load node:$src1, node:$src2, node:$src3), [{
639 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
640 (masked_load node:$src1, node:$src2, node:$src3), [{
646 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
647 (masked_load node:$src1, node:$src2, node:$src3), [{
653 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
654 (masked_load node:$src1, node:$src2, node:$src3), [{
658 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
659 (masked_store node:$src1, node:$src2, node:$src3), [
[all...] |
| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_tgsi_emit.h | 207 struct src_register src2 )
213 emit_src( emit, src2 ));
222 struct src_register src2,
229 emit_src( emit, src2 ) &&
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8/include/isl/ |
| seq.h | 37 isl_int m2, isl_int *src2, unsigned len);
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/include/isl/ |
| seq.h | 37 isl_int m2, isl_int *src2, unsigned len);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600Instructions.td | 102 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2,R600_Pred:$p, variable_ops),
103 !strconcat(opName, " $dst, $src0, $src1, $src2"),
149 (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
150 !strconcat(opName, "$dst, $src0, $src1, $src2"),
447 (select R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
456 [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
458 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
459 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
464 [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
469 [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
[all...] |
