| /external/clang/test/Driver/ |
| no-sibling-calls.c | 3 // CHECK-NOSC: "-mdisable-tail-calls"
7 // CHECK-OSC-NOT: "-mdisable-tail-calls"
|
| /external/llvm/test/CodeGen/ARM/ |
| PR15053.ll | 9 %0 = tail call { i32, i32 } @llvm.arm.ldrexd(i8* undef) nounwind
11 %2 = tail call i32 @llvm.arm.strexd(i32 %1, i32 undef, i8* undef) nounwind
|
| ghc-tcreturn-lowered.ll | 9 tail call ghccc void @g()
19 tail call ghccc void() %func()
|
| inlineasm4.ll | 5 %0 = tail call double asm "mov ${0:R}, #4\0A", "=&r"()
13 %0 = tail call double asm "mov ${0:Q}, #4\0A", "=&r"()
|
| intrinsics.ll | 7 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
9 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
11 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
13 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
15 tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
17 tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
19 tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
21 tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
|
| /external/llvm/test/CodeGen/Mips/ |
| inlineasm_constraint.ll | 10 tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind
16 tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind
22 tail call i32 asm sideeffect "addiu $0,$1,$2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind
28 tail call i16 asm sideeffect "addu $0,$1,$2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind
34 tail call i32 asm sideeffect "add $0,$1,$3\0A\09", "=r,r,L,r"(i32 7, i32 1048576, i32 0) nounwind
40 tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,N"(i32 7, i32 -3) nounwind
46 tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,O"(i32 7, i16 -3) nounwind
52 tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind
|
| /external/llvm/test/CodeGen/NVPTX/ |
| envreg.ll | 41 %val0 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg0()
43 %val1 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg1()
45 %val2 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg2()
47 %val3 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg3()
49 %val4 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg4()
51 %val5 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg5()
53 %val6 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg6()
55 %val7 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg7()
57 %val8 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg8()
59 %val9 = tail call i32 @llvm.nvvm.read.ptx.sreg.envreg9(
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| htm.ll | 7 %0 = tail call i32 @llvm.ppc.tbegin(i32 0)
22 %0 = tail call i32 @llvm.ppc.tend(i32 0)
34 %0 = tail call i32 @llvm.ppc.tabort(i32 0)
35 %1 = tail call i32 @llvm.ppc.tabortdc(i32 0, i32 1, i32 2)
36 %2 = tail call i32 @llvm.ppc.tabortdci(i32 0, i32 1, i32 2)
37 %3 = tail call i32 @llvm.ppc.tabortwc(i32 0, i32 1, i32 2)
38 %4 = tail call i32 @llvm.ppc.tabortwci(i32 0, i32 1, i32 2)
57 %0 = tail call i32 @llvm.ppc.tendall()
58 %1 = tail call i32 @llvm.ppc.tresume()
59 %2 = tail call i32 @llvm.ppc.tsuspend(
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| 20090313-signext.ll | 10 %0 = tail call signext i16 @h() nounwind
12 tail call void @g(i32 %1) nounwind
|
| inline-asm-2addr.ll | 5 %asmtmp = tail call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i64 %a) nounwind ; <i64> [#uses=1]
6 %asmtmp1 = tail call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i64 %b) nounwind ; <i64> [#uses=1]
|
| lzcnt.ll | 9 %tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 false )
16 %tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 false )
23 %tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 false )
30 %tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 false )
37 %tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 true )
44 %tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 true )
51 %tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true )
58 %tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 true )
|
| non-lazy-bind.ll | 18 tail call void @not()
25 tail call void @lazy()
|
| pr3250.ll | 8 %0 = tail call i32 (...) @safe_div_(i32 %p_107, i32 1) nounwind
12 %3 = tail call i32 @safe_sub_func_short_u_u(i16 signext 1, i16 signext
|
| sibcall-3.ll | 7 tail call void null(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind
14 tail call void null(i8* inreg %dst, i8* inreg %src) nounwind
|
| sse-fcopysign.ll | 4 %tmp = tail call float @copysignf( float %b, float %a )
11 %tmp = tail call double @copysign( double %a, double %tmp2 )
|
| stdcall-notailcall.ll | 9 tail call void @foo()
17 tail call void @foo()
|
| /external/llvm/test/Transforms/InstCombine/ |
| 2008-06-08-ICmpPHI.ll | 10 %tmp = tail call i32 (...) @bork( ) nounwind ; <i32> [#uses=0]
11 %tmp1 = tail call i32 (...) @bork( ) nounwind ; <i32> [#uses=0]
12 %tmp2 = tail call i32 (...) @bork( ) nounwind ; <i32> [#uses=1]
17 %tmp6 = tail call i32 (...) @bork( ) nounwind ; <i32> [#uses=0]
21 %tmp8 = tail call i32 (...) @bork( ) nounwind ; <i32> [#uses=0]
22 %tmp9 = tail call i32 (...) @bork( ) nounwind ; <i32> [#uses=0]
27 %tmp15 = tail call i32 (...) @bar( ) nounwind ; <i32> [#uses=0]
31 %tmp17 = tail call i32 (...) @zap( ) nounwind ; <i32> [#uses=1]
|
| x86-crc32-demanded.ll | 9 ; CHECK: tail call i64 @llvm.x86.sse42.crc32.64.64
12 %0 = tail call i64 @llvm.x86.sse42.crc32.64.64(i64 0, i64 4) nounwind
|
| /external/llvm/test/Transforms/ObjCARC/ |
| empty-block.ll | 23 %2 = tail call i8* @objc_retain(i8* %1) nounwind
30 %3 = tail call i8* @objc_retain(i8* %1) nounwind
31 tail call void @objc_release(i8* %1) nounwind, !clang.imprecise_release !0
32 %4 = tail call i8* @objc_autoreleaseReturnValue(i8* %1) nounwind
44 %2 = tail call i8* @objc_retain(i8* %1) nounwind
51 %3 = tail call i8* @objc_retain(i8* %1) nounwind
52 tail call void @objc_release(i8* %1) nounwind, !clang.imprecise_release !0
53 %4 = tail call i8* @objc_autoreleaseReturnValue(i8* %1) nounwind
|
| /external/llvm/test/MC/X86/ |
| stackmap-nops.ll | 28 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 0)
29 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 1, i32 1)
30 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 2, i32 2)
31 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 3)
32 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 4)
33 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 5, i32 5)
34 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 6, i32 6)
35 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 7, i32 7)
36 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 8, i32 8)
37 tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 9, i32 9
[all...] |
| /external/clang/test/CodeGen/ |
| 2006-09-18-fwrite-cast-crash.c | 10 ltmp_6203_92 = /*tail*/ ((unsigned (*) (signed char *, unsigned , unsigned ,
|
| /external/clang/test/CodeGenOpenCL/ |
| single-precision-constant.cl | 4 // CHECK: tail call float @llvm.fmuladd.f32(float %f, float 2.000000e+00, float 1.000000e+00)
|
| /external/llvm/test/Assembler/ |
| alignstack.ll | 10 tail call void asm sideeffect "mov", "~{dirflag},~{fpsr},~{flags}"() nounwind
18 tail call void asm sideeffect alignstack "mov", "~{dirflag},~{fpsr},~{flags}"() nounwind
26 tail call void asm alignstack "mov", "~{dirflag},~{fpsr},~{flags}"() nounwind
34 tail call void asm "mov", "~{dirflag},~{fpsr},~{flags}"() nounwind
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-inline-asm-zero-reg-error.ll | 7 tail call void asm sideeffect "USE($0)", "z"(i32 1) nounwind
|
| arm64-trap.ll | 5 tail call void @llvm.trap()
|
