| /external/llvm/test/Transforms/SimplifyCFG/PowerPC/ |
| cttz-ctlz-spec.ll | 8 ; CHECK-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
16 %0 = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
27 ; CHECK-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
35 %0 = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
|
| /external/llvm/test/Transforms/SimplifyCFG/ |
| phi-undef-loadstore.ll | 11 tail call void @bar() nounwind
19 tail call void @bar() nounwind
40 tail call void @bar() nounwind
48 tail call void @bar() nounwind
68 tail call void @bar() nounwind
76 tail call void @bar() nounwind
81 tail call void @bar() nounwind
95 tail call void @bar() nounwind
103 tail call void @bar() nounwind
|
| /external/llvm/test/Verifier/ |
| 2008-08-22-MemCpyAlignment.ll | 7 tail call void @llvm.memcpy.p0i8.p0i8.i64( i8* %a, i8* %src, i64 %len, i32 %align, i1 false) nounwind
|
| /external/marisa-trie/tools/ |
| marisa-build.cc | 30 " -T, --text-tail build a dictionary with text TAIL (default)\n"
31 " -b, --binary-tail build a dictionary with binary TAIL\n"
32 " -t, --without-tail build a dictionary without TAIL\n"
122 { "text-tail", 0, NULL, 'T' },
123 { "binary-tail", 0, NULL, 'b' },
124 { "without-tail", 0, NULL, 't' },
|
| /external/marisa-trie/v0_1_5/tools/ |
| marisa_alpha-build.cc | 30 " -T, --text-tail build a dictionary with text TAIL (default)\n"
31 " -b, --binary-tail build a dictionary with binary TAIL\n"
32 " -t, --without-tail build a dictionary without TAIL\n"
122 { "text-tail", 0, NULL, 'T' },
123 { "binary-tail", 0, NULL, 'b' },
124 { "without-tail", 0, NULL, 't' },
|
| /external/toybox/toys/posix/ |
| tail.c | 0 /* tail.c - copy last lines from input to stdout.
5 * See http://opengroup.org/onlinepubs/9699919799/utilities/tail.html
7 USE_TAIL(NEWTOY(tail, "?fc-n-[-cn]", TOYFLAG_USR|TOYFLAG_BIN))
9 config TAIL
10 bool "tail"
13 usage: tail [-n|c NUMBER] [-f] [FILE...]
23 bool "tail seek support"
25 depends on TAIL
71 // up a lot, but isn't applicable to all input (cat | tail).
|
| /external/valgrind/VEX/orig_amd64/ |
| SortedToOrig.hs | 17 rest = unwords (tail ws)
|
| /external/valgrind/coregrind/m_gdbserver/ |
| inferiors.c | 45 if (list->tail != NULL)
46 list->tail->next = new_inferior;
49 list->tail = new_inferior;
67 if (list->head != list->tail)
80 if (list->tail == entry)
81 list->tail = list->head;
94 if (list->tail == entry)
95 list->tail = *cur;
175 all_threads.head = all_threads.tail = NULL;
|
| /libcore/luni/src/test/java/libcore/java/util/logging/ |
| OldFormatterTest.java | 41 assertEquals("tail string is not empty", "", f.getTail(null));
53 assertEquals("tail string is not empty", "", f.getTail(null));
54 assertEquals("tail string is not empty", "", f.getTail(h));
56 assertEquals("tail string is not empty", "", f.getTail(h));
|
| OldXMLFormatterTest.java | 55 assertTrue("Tail string position should be more zero", formatter
60 assertEquals("Tail string with null handler should be equal expected value",
62 assertEquals("Tail string should be equal expected value", "</log>",
65 assertEquals("Tail string after publish() should be equal expected value",
|
| /external/llvm/test/CodeGen/Mips/ |
| dsp-r2.ll | 9 %3 = tail call i64 @llvm.mips.dpa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
21 %3 = tail call i64 @llvm.mips.dps.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
33 %3 = tail call i64 @llvm.mips.mulsa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
45 %3 = tail call i64 @llvm.mips.dpax.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
57 %3 = tail call i64 @llvm.mips.dpsx.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
69 %3 = tail call i64 @llvm.mips.dpaqx.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
81 %3 = tail call i64 @llvm.mips.dpaqx.sa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
93 %3 = tail call i64 @llvm.mips.dpsqx.s.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
105 %3 = tail call i64 @llvm.mips.dpsqx.sa.w.ph(i64 %a0, <2 x i16> %1, <2 x i16> %2)
117 %2 = tail call <2 x i16> @llvm.mips.addu.ph(<2 x i16> %0, <2 x i16> %1
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| stack-folding-mmx.ll | 6 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
15 %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm1},~{mm1},~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
24 %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm1},~{mm1},~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
33 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
42 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
51 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
65 %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
74 %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
83 %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"()
92 %1 = tail call x86_mmx asm sideeffect "nop", "=y,~{mm2},~{mm3},~{mm4},~{mm5},~{mm6},~{mm7}"(
[all...] |
| 3dnow-intrinsics.ll | 21 %1 = tail call x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx %0)
33 %2 = tail call x86_mmx @llvm.x86.3dnow.pfacc(x86_mmx %0, x86_mmx %1)
45 %2 = tail call x86_mmx @llvm.x86.3dnow.pfadd(x86_mmx %0, x86_mmx %1)
57 %2 = tail call x86_mmx @llvm.x86.3dnow.pfcmpeq(x86_mmx %0, x86_mmx %1)
69 %2 = tail call x86_mmx @llvm.x86.3dnow.pfcmpge(x86_mmx %0, x86_mmx %1)
81 %2 = tail call x86_mmx @llvm.x86.3dnow.pfcmpgt(x86_mmx %0, x86_mmx %1)
93 %2 = tail call x86_mmx @llvm.x86.3dnow.pfmax(x86_mmx %0, x86_mmx %1)
105 %2 = tail call x86_mmx @llvm.x86.3dnow.pfmin(x86_mmx %0, x86_mmx %1)
117 %2 = tail call x86_mmx @llvm.x86.3dnow.pfmul(x86_mmx %0, x86_mmx %1)
128 %1 = tail call x86_mmx @llvm.x86.3dnow.pfrcp(x86_mmx %0
[all...] |
| bmi.ll | 9 %tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 false )
16 %tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 false )
23 %tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 false )
31 %tmp = tail call i32 @llvm.cttz.i32(i32 %x1, i1 false )
38 %tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 false )
45 %tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 true )
52 %tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 true )
59 %tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true )
66 %tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 true )
98 %tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %y
[all...] |
| sibcall.ll | 15 tail call void @foo() nounwind
31 %0 = tail call i32 @foo2() nounwind
47 %0 = tail call i32 @foo3() nounwind
66 tail call void %x(i32 0) nounwind
86 tail call void %x() nounwind
108 %2 = tail call i32 @t6(i32 %1) nounwind ssp
112 %3 = tail call i32 @bar(i32 %x) nounwind
128 %0 = tail call i32 @bar2(i32 %a, i32 %b, i32 %c) nounwind
144 %0 = tail call signext i16 @bar3() nounwind ; <i16> [#uses=1]
161 %1 = tail call signext i16 %0(i32 0) nounwin
[all...] |
| x86-64-psub.ll | 12 %call = tail call { i64, double } @getFirstParam()
14 %call2 = tail call { i64, double } @getSecondParam()
22 %6 = tail call x86_mmx @llvm.x86.mmx.psub.b(x86_mmx %3, x86_mmx %5) nounwind
40 %call = tail call { i64, double } @getFirstParam()
42 %call2 = tail call { i64, double } @getSecondParam()
50 %6 = tail call x86_mmx @llvm.x86.mmx.psub.w(x86_mmx %3, x86_mmx %5) nounwind
69 %call = tail call { i64, double } @getFirstParam()
71 %call2 = tail call { i64, double } @getSecondParam()
79 %6 = tail call x86_mmx @llvm.x86.mmx.psub.d(x86_mmx %3, x86_mmx %5) nounwind
97 %call = tail call { i64, double } @getFirstParam(
[all...] |
| stack-folding-int-sse42.ll | 14 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
23 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
32 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
41 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
50 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
59 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{flags}"()
74 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
86 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
95 %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
108 %3 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{ (…)
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| 2012-08-27-CopyPhysRegCrash.ll | 22 %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* null, i32 1)
25 %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %9, i32 1)
27 %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %6, i32 1)
31 %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %15, i32 1)
43 %28 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %26) nounwind
46 %31 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> undef, <8 x i16> %30) nounwind
57 %42 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %36) nounwind
58 %43 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %41) nounwind
62 %47 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %31, <8 x i16> %46) nounwind
66 %51 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %50, <4 x i16> undef) nounwin
[all...] |
| /external/clang/test/CodeGen/ |
| builtins-arm-exclusive.c | 17 // CHECK: [[OLDVAL:%.*]] = tail call i32 @llvm.arm.ldrex.p0i32(i32* %addr)
19 // CHECK: [[FAILURE:%.*]] = tail call i32 @llvm.arm.strex.p0i32(i32 [[INC]], i32* %addr)
24 // CHECK-ARM64: [[OLDVAL:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
27 // CHECK-ARM64: [[FAILURE:%.*]] = tail call i32 @llvm.aarch64.stxr.p0i32(i64 [[TRUNC]], i32* %addr)
40 // CHECK: [[INTRES:%.*]] = tail call i32 @llvm.arm.ldrex.p0i8(i8* %addr)
43 // CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
50 // CHECK: [[INTRES:%.*]] = tail call i32 @llvm.arm.ldrex.p0i16(i16* [[ADDR16]])
55 // CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i16(i16* [[ADDR16]])
65 // CHECK-ARM64: [[INTRES:%.*]] = tail call i64 @llvm.aarch64.ldxr.p0i32(i32* [[ADDR32]])
82 // CHECK: [[INTRES:%.*]] = tail call i32 @llvm.arm.ldrex.p0i32(i32* [[INTADDR]]
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vaddv.ll | 9 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a1)
20 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a2)
32 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a1)
43 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a2)
56 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a1)
66 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a2)
77 %vaddv.i = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a1)
87 %0 = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a2)
98 %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a1)
109 %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a2
[all...] |
| arm64-arith-saturating.ll | 8 %vqadd.i = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %vecext, i32 %vecext1) nounwind
17 %vqadd.i = tail call i64 @llvm.aarch64.neon.sqadd.i64(i64 %vecext, i64 %vecext1) nounwind
26 %vqadd.i = tail call i32 @llvm.aarch64.neon.uqadd.i32(i32 %vecext, i32 %vecext1) nounwind
35 %vqadd.i = tail call i64 @llvm.aarch64.neon.uqadd.i64(i64 %vecext, i64 %vecext1) nounwind
49 %vqsub.i = tail call i32 @llvm.aarch64.neon.sqsub.i32(i32 %vecext, i32 %vecext1) nounwind
58 %vqsub.i = tail call i64 @llvm.aarch64.neon.sqsub.i64(i64 %vecext, i64 %vecext1) nounwind
67 %vqsub.i = tail call i32 @llvm.aarch64.neon.uqsub.i32(i32 %vecext, i32 %vecext1) nounwind
76 %vqsub.i = tail call i64 @llvm.aarch64.neon.uqsub.i64(i64 %vecext, i64 %vecext1) nounwind
90 %vqabs.i = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %vecext) nounwind
99 %vqabs.i = tail call i64 @llvm.aarch64.neon.sqabs.i64(i64 %vecext) nounwin
[all...] |
| /external/llvm/test/CodeGen/Hexagon/vect/ |
| vect-vshifts.ll | 24 %9 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %8, i32 1)
26 %11 = tail call i64 @llvm.hexagon.A2.combinew(i32 -1, i32 -1)
40 %14 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %13, i32 31)
45 %17 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %14, i64 %16)
47 %19 = tail call i64 @llvm.hexagon.C2.vmux(i32 %17, i64 %13, i64 %18)
48 %20 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %19, i32 %gb)
69 %25 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %24, i32 31)
74 %28 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %25, i64 %27)
76 %30 = tail call i64 @llvm.hexagon.C2.vmux(i32 %28, i64 %24, i64 %29)
77 %31 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %30, i32 %gb
[all...] |
| /external/llvm/test/Transforms/SLPVectorizer/X86/ |
| intrinsic.ll | 19 %call = tail call double @llvm.fabs.f64(double %mul) nounwind readnone
25 %call5 = tail call double @llvm.fabs.f64(double %mul5) nounwind readnone
44 %call0 = tail call float @llvm.copysign.f32(float %0, float %1) nounwind readnone
51 %call1 = tail call float @llvm.copysign.f32(float %2, float %3) nounwind readnone
59 %call2 = tail call float @llvm.copysign.f32(float %4, float %5) nounwind readnone
67 %call3 = tail call float @llvm.copysign.f32(float %6, float %7) nounwind readnone
81 %call1 = tail call i32 @llvm.bswap.i32(i32 %add1) nounwind readnone
88 %call2 = tail call i32 @llvm.bswap.i32(i32 %add2) nounwind readnone
95 %call3 = tail call i32 @llvm.bswap.i32(i32 %add3) nounwind readnone
102 %call4 = tail call i32 @llvm.bswap.i32(i32 %add4) nounwind readnon
[all...] |
| /libcore/luni/src/main/java/java/util/concurrent/ |
| ConcurrentLinkedQueue.java | 25 * The <em>tail</em> of the queue is that element that has been on the
27 * are inserted at the tail of the queue, and the queue retrieval
93 * reached in O(1) time from tail, but tail is merely an
117 * Both head and tail are permitted to lag. In fact, failing to
121 * that is, we update head/tail when the current pointer appears
124 * Since head and tail are updated concurrently and independently,
125 * it is possible for tail to lag behind head (why not)?
140 * Both head and tail may or may not point to a Node with a
142 * be null. Upon creation, both head and tail refer to a dumm
218 private transient volatile Node<E> tail; field in class:ConcurrentLinkedQueue
[all...] |
| /external/clang/test/CXX/temp/temp.decls/temp.variadic/ |
| example-bind.cpp | 59 template<typename Head, typename... Tail>
60 class tuple<Head, Tail...> : private tuple<Tail...> {
61 typedef tuple<Tail...> inherited;
69 typename add_const_reference<Tail>::type... vtail)
74 : m_head(other.head()), inherited(other.tail()) { }
79 tail() = other.tail();
85 inherited& tail() { return *this; } function in class:tuple
86 const inherited& tail() const { return *this; function in class:tuple
[all...] |
