| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 97 const TargetRegisterClass *
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| /external/llvm/lib/Target/Mips/ |
| MipsOptimizePICCall.cpp | 119 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
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| MipsFastISel.cpp | 140 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
160 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
258 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
269 const TargetRegisterClass *RC) {
298 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
304 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
319 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
[all...] |
| Mips16InstrInfo.cpp | 96 const TargetRegisterClass *RC,
114 const TargetRegisterClass *RC,
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| MipsISelLowering.h | 491 std::pair<unsigned, const TargetRegisterClass *>
494 std::pair<unsigned, const TargetRegisterClass *>
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| Mips16ISelDAGToDAG.cpp | 78 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
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| MipsSEInstrInfo.cpp | 182 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
224 unsigned DestReg, int FI, const TargetRegisterClass *RC,
390 const TargetRegisterClass *RC = STI.isABI_N64() ?
|
| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.h | 218 const TargetRegisterClass *getIndirectAddrRegClass() const override;
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| AMDGPUISelLowering.h | 204 const TargetRegisterClass *RC,
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| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 83 std::pair<unsigned, const TargetRegisterClass *>
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| SparcRegisterInfo.cpp | 89 const TargetRegisterClass*
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| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 175 std::pair<unsigned, const TargetRegisterClass *>
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| XCoreFrameLowering.cpp | 432 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
460 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
567 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
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| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 611 const TargetRegisterClass *RC =
647 const TargetRegisterClass *RC =
685 const TargetRegisterClass *FirstRC =
844 const TargetRegisterClass *RC,
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 486 const TargetRegisterClass *RC,
523 const TargetRegisterClass *RC,
533 const TargetRegisterClass *RC,
563 const TargetRegisterClass *RC,
663 const TargetRegisterClass *TRC;
[all...] |
| HexagonHardwareLoops.cpp | 761 const TargetRegisterClass *RC = MRI->getRegClass(R);
766 const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineCSE.cpp | 155 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
570 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
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| MachineSink.cpp | 157 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
158 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
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| LocalStackSlotAllocation.cpp | 395 const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF);
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| MachineSSAUpdater.cpp | 116 const TargetRegisterClass *RC,
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| MachineVerifier.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 708 std::pair<unsigned, const TargetRegisterClass *>
858 std::pair<const TargetRegisterClass *, uint8_t>
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineFrameInfo.h | 25 class TargetRegisterClass;
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXAsmPrinter.h | 249 typedef DenseMap<const TargetRegisterClass *, VRegMap> VRegRCMap;
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 237 std::pair<unsigned, const TargetRegisterClass *>
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