| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 29 class TargetRegisterClass;
118 BitVector getRegsAvailable(const TargetRegisterClass *RC);
122 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
151 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
153 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
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| FastISel.h | 384 const TargetRegisterClass *RC);
389 const TargetRegisterClass *RC, unsigned Op0,
395 const TargetRegisterClass *RC, unsigned Op0,
401 const TargetRegisterClass *RC, unsigned Op0,
408 const TargetRegisterClass *RC, unsigned Op0,
414 const TargetRegisterClass *RC, unsigned Op0,
420 const TargetRegisterClass *RC, unsigned Op0,
426 const TargetRegisterClass *RC, unsigned Op0,
433 const TargetRegisterClass *RC, unsigned Op0,
440 const TargetRegisterClass *RC, uint64_t Imm)
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIFixSGPRCopies.cpp | 88 const TargetRegisterClass *inferRegClassFromUses(const SIRegisterInfo *TRI,
92 const TargetRegisterClass *inferRegClassFromDef(const SIRegisterInfo *TRI,
134 const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromUses(
140 const TargetRegisterClass *RC
160 const TargetRegisterClass *SIFixSGPRCopies::inferRegClassFromDef(
166 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg);
186 const TargetRegisterClass *DstRC
191 const TargetRegisterClass *SrcRC;
230 const TargetRegisterClass *RC
236 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg
[all...] |
| R600RegisterInfo.cpp | 49 for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
67 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
76 const TargetRegisterClass *RC) const {
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| SIInstrInfo.h | 32 const TargetRegisterClass *SuperRC,
34 const TargetRegisterClass *SubRC) const;
38 const TargetRegisterClass *SuperRC,
40 const TargetRegisterClass *SubRC) const;
45 const TargetRegisterClass *RC,
102 const TargetRegisterClass *RC,
108 const TargetRegisterClass *RC,
116 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
137 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
249 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI
[all...] |
| AMDGPURegisterInfo.h | 40 virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
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| AMDGPUInstrInfo.h | 79 const TargetRegisterClass *RC,
84 const TargetRegisterClass *RC,
131 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
166 virtual const TargetRegisterClass *getIndirectAddrRegClass() const = 0;
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.h | 46 const TargetRegisterClass* const*
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| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.h | 93 const TargetRegisterClass *RC,
101 const TargetRegisterClass *RC,
109 const TargetRegisterClass *RC,
116 const TargetRegisterClass *RC,
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| MipsMachineFunction.cpp | 77 const TargetRegisterClass *RC =
98 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
104 const TargetRegisterClass *RC =
137 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
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| MipsSEISelLowering.h | 28 void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
32 const TargetRegisterClass *RC);
51 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
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| MipsSEInstrInfo.h | 54 const TargetRegisterClass *RC,
61 const TargetRegisterClass *RC,
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| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.h | 35 const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
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| SparcInstrInfo.h | 88 const TargetRegisterClass *RC,
94 const TargetRegisterClass *RC,
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600RegisterInfo.cpp | 45 for (TargetRegisterClass::iterator I = AMDGPU::R600_CReg32RegClass.begin(),
58 const TargetRegisterClass *
59 R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
107 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
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| AMDGPUInstrInfo.cpp | 126 const TargetRegisterClass *RC,
135 const TargetRegisterClass *RC,
233 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
249 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
250 const TargetRegisterClass * newRegClass = RI.getISARegClass(oldRegClass);
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| /external/llvm/include/llvm/Target/ |
| TargetSubtargetInfo.h | 31 class TargetRegisterClass;
55 typedef SmallVectorImpl<const TargetRegisterClass *> RegClassVector;
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| /external/llvm/lib/CodeGen/ |
| CriticalAntiDepBreaker.h | 51 std::vector<const TargetRegisterClass*> Classes;
103 const TargetRegisterClass *RC,
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| CriticalAntiDepBreaker.cpp | 64 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
79 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
109 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
116 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
178 const TargetRegisterClass *NewRC = nullptr;
188 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
197 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
198 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
203 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
217 Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1))
[all...] |
| AggressiveAntiDepBreaker.h | 43 const TargetRegisterClass *RC;
155 typedef std::map<const TargetRegisterClass *, unsigned> RenameOrderType;
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| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.h | 50 const TargetRegisterClass *RC,
56 const TargetRegisterClass *RC,
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| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 64 const TargetRegisterClass *RC,
69 const TargetRegisterClass *RC,
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXRegisterInfo.cpp | 29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) {
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) {
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| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 73 const TargetRegisterClass *RC,
79 const TargetRegisterClass *RC,
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| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.h | 66 const TargetRegisterClass *
69 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
72 const TargetRegisterClass *
73 getLargestLegalSuperClass(const TargetRegisterClass *RC,
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