| /external/clang/test/CodeGen/ |
| 2007-04-13-InlineAsmStruct2.c | 7 __asm__ volatile("foo %0\n" :: "r"(bar));
|
| 2008-12-23-AsmIntPointerTie.c | 7 __asm__ __volatile__ ("%0 %1 " : "=r" (a): "0" (b));
|
| arm-asm-warn.c | 7 __asm__ volatile("mcr p15, 0, %1, c9, c12, 5;"
11 __asm__ volatile("foo %0, %1"
15 __asm__ volatile("ldrb %0, [%1]" : "=r" (y) : "r" (x)); // no warning
25 __asm__("vldm %[a], { %q[r0], %q[r1], %q[r2], %q[r3] }"
|
| mips-constraint-regs.c | 15 __asm__ __volatile__(
26 __asm__ __volatile__(
39 __asm__ __volatile__(
|
| /external/valgrind/VEX/switchback/ |
| test_simple.c | 5 __asm__ __volatile__ ("addi 17, 14, 5");
|
| /external/valgrind/memcheck/tests/amd64/ |
| sh-mem-vec128.c | 11 __asm__ __volatile__(
|
| sh-mem-vec256.c | 14 __asm__ __volatile__(
|
| /external/valgrind/memcheck/tests/x86/ |
| sh-mem-vec128.c | 11 __asm__ __volatile__(
|
| /external/valgrind/none/tests/amd64/ |
| tm1.c | 15 __asm__ __volatile__(
18 __asm__ __volatile__(
43 __asm__ __volatile__(
55 __asm__ __volatile__(
62 __asm__ __volatile__( "xabort $0x1" );
|
| /external/valgrind/none/tests/mips64/ |
| cvm_bbit.c | 8 __asm__ volatile(
20 __asm__ volatile(
42 __asm__ volatile(
57 __asm__ volatile(
|
| test_fcsr.c | 7 __asm__ volatile("cfc1 $a1, $31" "\n\t"
|
| /external/valgrind/none/tests/ppc64/ |
| tw_td.c | 34 __asm__ __volatile__("tw 0, %0,%1"
38 __asm__ __volatile__("tw 1, %0,%1"
42 __asm__ __volatile__("tw 2, %0,%1"
46 __asm__ __volatile__("tw 3, %0,%1"
50 __asm__ __volatile__("tw 4, %0,%1"
54 __asm__ __volatile__("tw 5, %0,%1"
58 __asm__ __volatile__("tw 6, %0,%1"
62 __asm__ __volatile__("tw 7, %0,%1"
66 __asm__ __volatile__("tw 8, %0,%1"
70 __asm__ __volatile__("tw 9, %0,%1
[all...] |
| /development/ndk/platforms/android-3/arch-arm/include/asm/ |
| locks.h | 17 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
19 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" "1: ldrex lr, [%1]\n" " sub lr, lr, %2\n" " strex ip, lr, [%1]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
21 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " cmp lr, #0\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
26 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
28 #define __up_op_write(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_write\n" "1: ldrex lr, [%0]\n" " adds lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); })
32 #define __up_op_read(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_read\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " moveq ip, %0\n" " bleq " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" (…)
[all...] |
| /external/fio/arch/ |
| arch-mips.h | 21 #define read_barrier() __asm__ __volatile__("": : :"memory")
22 #define write_barrier() __asm__ __volatile__("": : :"memory")
23 #define nop __asm__ __volatile__("": : :"memory")
|
| /external/valgrind/none/tests/x86/ |
| movx.c | 7 __asm__ __volatile__(
20 __asm__ __volatile__(
33 __asm__ __volatile__(
46 __asm__ __volatile__(
59 __asm__ __volatile__(
72 __asm__ __volatile__(
85 __asm__ __volatile__(
98 __asm__ __volatile__(
111 __asm__ __volatile__(
124 __asm__ __volatile__
[all...] |
| /prebuilts/ndk/4/platforms/android-3/arch-arm/usr/include/asm/ |
| locks.h | 17 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
19 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" "1: ldrex lr, [%1]\n" " sub lr, lr, %2\n" " strex ip, lr, [%1]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
21 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " cmp lr, #0\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
26 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
28 #define __up_op_write(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_write\n" "1: ldrex lr, [%0]\n" " adds lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); })
32 #define __up_op_read(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_read\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " moveq ip, %0\n" " bleq " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" (…)
[all...] |
| /prebuilts/ndk/4/platforms/android-4/arch-arm/usr/include/asm/ |
| locks.h | 17 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
19 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" "1: ldrex lr, [%1]\n" " sub lr, lr, %2\n" " strex ip, lr, [%1]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
21 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " cmp lr, #0\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
26 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
28 #define __up_op_write(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_write\n" "1: ldrex lr, [%0]\n" " adds lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); })
32 #define __up_op_read(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_read\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " moveq ip, %0\n" " bleq " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" (…)
[all...] |
| /prebuilts/ndk/4/platforms/android-5/arch-arm/usr/include/asm/ |
| locks.h | 17 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
19 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" "1: ldrex lr, [%1]\n" " sub lr, lr, %2\n" " strex ip, lr, [%1]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
21 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " cmp lr, #0\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
26 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
28 #define __up_op_write(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_write\n" "1: ldrex lr, [%0]\n" " adds lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); })
32 #define __up_op_read(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_read\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " moveq ip, %0\n" " bleq " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" (…)
[all...] |
| /prebuilts/ndk/4/platforms/android-8/arch-arm/usr/include/asm/ |
| locks.h | 17 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
19 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" "1: ldrex lr, [%1]\n" " sub lr, lr, %2\n" " strex ip, lr, [%1]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
21 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " cmp lr, #0\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
26 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
28 #define __up_op_write(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_write\n" "1: ldrex lr, [%0]\n" " adds lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); })
32 #define __up_op_read(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_read\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " moveq ip, %0\n" " bleq " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" (…)
[all...] |
| /prebuilts/ndk/5/platforms/android-3/arch-arm/usr/include/asm/ |
| locks.h | 17 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
19 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" "1: ldrex lr, [%1]\n" " sub lr, lr, %2\n" " strex ip, lr, [%1]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
21 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " cmp lr, #0\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
26 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
28 #define __up_op_write(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_write\n" "1: ldrex lr, [%0]\n" " adds lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); })
32 #define __up_op_read(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_read\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " moveq ip, %0\n" " bleq " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" (…)
[all...] |
| /prebuilts/ndk/6/platforms/android-3/arch-arm/usr/include/asm/ |
| locks.h | 17 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
19 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" "1: ldrex lr, [%1]\n" " sub lr, lr, %2\n" " strex ip, lr, [%1]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
21 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " cmp lr, #0\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
26 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
28 #define __up_op_write(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_write\n" "1: ldrex lr, [%0]\n" " adds lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); })
32 #define __up_op_read(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_read\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " moveq ip, %0\n" " bleq " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" (…)
[all...] |
| /prebuilts/ndk/7/platforms/android-14/arch-arm/usr/include/asm/ |
| locks.h | 17 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
19 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" "1: ldrex lr, [%1]\n" " sub lr, lr, %2\n" " strex ip, lr, [%1]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
21 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " cmp lr, #0\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
26 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
28 #define __up_op_write(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_write\n" "1: ldrex lr, [%0]\n" " adds lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); })
32 #define __up_op_read(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_read\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " moveq ip, %0\n" " bleq " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" (…)
[all...] |
| /prebuilts/ndk/7/platforms/android-3/arch-arm/usr/include/asm/ |
| locks.h | 17 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
19 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" "1: ldrex lr, [%1]\n" " sub lr, lr, %2\n" " strex ip, lr, [%1]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
21 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " cmp lr, #0\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
26 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
28 #define __up_op_write(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_write\n" "1: ldrex lr, [%0]\n" " adds lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); })
32 #define __up_op_read(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_read\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " moveq ip, %0\n" " bleq " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" (…)
[all...] |
| /prebuilts/ndk/7/platforms/android-4/arch-arm/usr/include/asm/ |
| locks.h | 17 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
19 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" "1: ldrex lr, [%1]\n" " sub lr, lr, %2\n" " strex ip, lr, [%1]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
21 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " cmp lr, #0\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
26 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
28 #define __up_op_write(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_write\n" "1: ldrex lr, [%0]\n" " adds lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); })
32 #define __up_op_read(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_read\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " moveq ip, %0\n" " bleq " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" (…)
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| /prebuilts/ndk/7/platforms/android-5/arch-arm/usr/include/asm/ |
| locks.h | 17 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
19 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" "1: ldrex lr, [%1]\n" " sub lr, lr, %2\n" " strex ip, lr, [%1]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
21 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " cmp lr, #0\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
26 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" "1: ldrex lr, [%0]\n" " sub lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
28 #define __up_op_write(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_write\n" "1: ldrex lr, [%0]\n" " adds lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); })
32 #define __up_op_read(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_read\n" "1: ldrex lr, [%0]\n" " add lr, lr, %1\n" " strex ip, lr, [%0]\n" " teq ip, #0\n" " bne 1b\n" " teq lr, #0\n" " moveq ip, %0\n" " bleq " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
36 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
38 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
40 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
45 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" (…)
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