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  /external/llvm/test/MC/ARM/
symbol-variants.s 53 .word f15(target1)
55 @CHECK: 3c R_ARM_TARGET1 f15
ldr-pseudo.s 146 @ CHECK-LABEL: f15:
147 f15: label
  /external/valgrind/VEX/priv/
host_s390_isel.c 1249 HReg op_hi, op_lo, f13, f15; local
1283 HReg op_hi, op_lo, f13, f15; local
1351 HReg op1_hi, op1_lo, op2_hi, op2_lo, f12, f13, f14, f15, cc_s390; local
1398 HReg op1_hi, op1_lo, op2_hi, op2_lo, f12, f13, f14, f15, cc_s390; local
1604 HReg op_hi, op_lo, f13, f15; local
2001 HReg op1_hi, op1_lo, op2_hi, op2_lo, f12, f13, f14, f15; local
2045 HReg op_hi, op_lo, f12, f13, f14, f15; local
2156 HReg op_hi, op_lo, op, f12, f13, f14, f15; local
2463 HReg op_hi, op_lo, f12, f13, f14, f15; local
2653 HReg op1_hi, op1_lo, op2_hi, op2_lo, f9, f11, f12, f13, f14, f15; local
2740 HReg op1_hi, op1_lo, op2, f9, f11, f13, f15; local
3059 HReg op_hi, op_lo, f12, f13, f14, f15; local
    [all...]
  /external/valgrind/coregrind/m_dispatch/
dispatch-s390x-linux.S 95 /* Save fprs: ABI: f8...f15 */
103 std %f15,160+56(SP)
162 ld %f15,160+56(SP)
  /ndk/tests/device/test-stlport_shared-exception/jni/
registers1.cpp 42 float f15 = *fsrc++ + 1.0f; local
89 *fdest++ = f15;
  /ndk/tests/device/test-stlport_static-exception/jni/
registers1.cpp 42 float f15 = *fsrc++ + 1.0f; local
89 *fdest++ = f15;
  /external/clang/test/Analysis/
array-struct.c 139 void f15() { function
  /external/clang/test/CodeGenCXX/
aarch64-mangle-neon-vectors.cpp 68 void f15(int8x16_t) {} function
debug-info-line.cpp 193 void f15(foo *f) { function
  /external/llvm/test/MC/SystemZ/
insn-good.s 26 #CHECK: adb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x1a]
34 adb %f15, 0
37 #CHECK: adbr %f0, %f15 # encoding: [0xb3,0x1a,0x00,0x0f]
39 #CHECK: adbr %f15, %f0 # encoding: [0xb3,0x1a,0x00,0xf0]
42 adbr %f0, %f15
44 adbr %f15, %f0
52 #CHECK: aeb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x0a]
60 aeb %f15, 0
63 #CHECK: aebr %f0, %f15 # encoding: [0xb3,0x0a,0x00,0x0f]
65 #CHECK: aebr %f15, %f0 # encoding: [0xb3,0x0a,0x00,0xf0
    [all...]
  /external/clang/test/CodeGen/
arm-arguments.c 89 // APCS-GNU-LABEL: define void @f15()
90 // AAPCS-LABEL: define arm_aapcscc void @f15()
91 void f15(struct s7 a0) {} function
exprs.c 154 // CHECK-LABEL: define void @f15
155 void f15() {
struct.c 163 int f15() { function
  /external/v8/test/webkit/
toString-elision-trailing-comma.js 85 function f15() { function
130 testToStringAndLength("f15", 2);
  /external/llvm/test/MC/Mips/mips1/
valid.s 36 cvt.s.w $f22,$f15
41 div.s $f4,$f5,$f15
82 neg.s $f1,$f15
invalid-mips3.s 15 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
68 trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/valgrind/none/tests/ppc32/
test_dfp2.c 36 register double f15 __asm__ ("fr15");
475 f15 = d0x;
549 f15 = d0x;
test_dfp1.c 30 register double f15 __asm__ ("fr15");
353 f15 = d0x;
  /external/llvm/test/MC/AArch64/
ldr-pseudo.s 156 // CHECK-LABEL: f15:
157 f15: label
  /external/llvm/test/MC/ELF/
cfi.s 89 f15: label
  /external/llvm/test/MC/Mips/mips2/
valid.s 50 cvt.s.w $f22,$f15
55 div.s $f4,$f5,$f15
102 neg.s $f1,$f15
170 trunc.w.d $f22,$f15
  /external/llvm/test/MC/Mips/mips32/
valid.s 57 cvt.s.w $f22,$f15
63 div.s $f4,$f5,$f15
130 neg.s $f1,$f15
200 trunc.w.d $f22,$f15
  /external/llvm/test/MC/PowerPC/
ppc64-regs.s 54 #CHECK: .cfi_offset f15, 420
171 .cfi_offset f15,420
  /external/llvm/test/MC/Mips/mips3/
valid.s 53 cvt.l.d $f24,$f15
56 cvt.s.l $f15,$f30
57 cvt.s.w $f22,$f15
74 div.s $f4,$f5,$f15
159 neg.s $f1,$f15
233 trunc.w.d $f22,$f15
  /external/llvm/test/MC/Mips/mips4/
valid.s 57 cvt.l.d $f24,$f15
60 cvt.s.l $f15,$f30
61 cvt.s.w $f22,$f15
78 div.s $f4,$f5,$f15
181 neg.s $f1,$f15
262 trunc.w.d $f22,$f15

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