| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 57 cvt.l.d $f24,$f15
60 cvt.s.l $f15,$f30
61 cvt.s.w $f22,$f15
78 div.s $f4,$f5,$f15
182 neg.s $f1,$f15
264 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 59 cvt.l.d $f24,$f15
62 cvt.s.l $f15,$f30
63 cvt.s.w $f22,$f15
83 div.s $f4,$f5,$f15
196 neg.s $f1,$f15
281 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 59 cvt.l.d $f24,$f15
62 cvt.s.l $f15,$f30
63 cvt.s.w $f22,$f15
85 div.s $f4,$f5,$f15
212 neg.s $f1,$f15
307 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 59 cvt.l.d $f24,$f15
62 cvt.s.l $f15,$f30
63 cvt.s.w $f22,$f15
85 div.s $f4,$f5,$f15
212 neg.s $f1,$f15
307 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 59 cvt.l.d $f24,$f15
62 cvt.s.l $f15,$f30
63 cvt.s.w $f22,$f15
85 div.s $f4,$f5,$f15
212 neg.s $f1,$f15
307 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/SystemZ/ |
| insn-good-z196.s | 143 #CHECK: cdlfbr %f15, 0, %r0, 0 # encoding: [0xb3,0x91,0x00,0xf0]
150 cdlfbr %f15, 0, %r0, 0
157 #CHECK: cdlgbr %f15, 0, %r0, 0 # encoding: [0xb3,0xa1,0x00,0xf0]
164 cdlgbr %f15, 0, %r0, 0
171 #CHECK: celfbr %f15, 0, %r0, 0 # encoding: [0xb3,0x90,0x00,0xf0]
178 celfbr %f15, 0, %r0, 0
185 #CHECK: celgbr %f15, 0, %r0, 0 # encoding: [0xb3,0xa0,0x00,0xf0]
192 celgbr %f15, 0, %r0, 0
232 #CHECK: clfdbr %r0, 0, %f15, 0 # encoding: [0xb3,0x9d,0x00,0x0f]
239 clfdbr %r0, 0, %f15,
[all...] |
| regs-bad.s | 155 #CHECK: lxr %f0,%f15
176 lxr %f0,%f15
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 56 cvt.l.d $f24,$f15
59 cvt.s.w $f22,$f15
67 div.s $f4,$f5,$f15
148 neg.s $f1,$f15
237 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 56 cvt.l.d $f24,$f15
59 cvt.s.w $f22,$f15
67 div.s $f4,$f5,$f15
148 neg.s $f1,$f15
237 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 56 cvt.l.d $f24,$f15
59 cvt.s.w $f22,$f15
67 div.s $f4,$f5,$f15
148 neg.s $f1,$f15
237 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips4.s | 15 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
88 trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 15 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
86 trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips2.s | 46 trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/ARM/ |
| ldr-pseudo-darwin.s | 146 @ CHECK-LABEL: f15:
147 f15: label
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 8 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/clang/test/Analysis/ |
| dead-stores.c | 146 void f15(unsigned x, unsigned y) { function
|
| /external/clang/test/CodeGen/ |
| x86_32-arguments-darwin.c | 77 // CHECK: <2 x i64> @f15()
88 T15 f15(void) { while (1) {} } function
|
| x86_64-arguments.c | 83 // CHECK: define void @f15({{.*}}, i8* %X)
84 void f15(int a, int b, int c, int d, int e, int f, void *X) {} function
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 11 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 13 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 13 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/v8/test/mjsunit/harmony/ |
| block-let-crankshaft.js | 34 f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25, f26,
108 function f15() { function
|
| /external/valgrind/none/tests/mips32/ |
| MoveIns.c | 298 TESTINSNMOVE("mfc1 $s6, $f15", 60, f15, s6);
327 TESTINSNMOVEt("mtc1 $s6, $f15", 60, f15, s6);
356 TESTINSNMOVE1s("mov.s $f14, $f15", 60, f14, f15);
357 TESTINSNMOVE1s("mov.s $f15, $f16", 64, f15, f16);
|
| /external/v8/src/mips/ |
| simulator-mips.h | 144 f12, f13, f14, f15, // f12 and f14 are arguments FPURegisters. enumerator in enum:v8::internal::Simulator::FPURegister
|
| /external/valgrind/none/tests/ppc32/ |
| test_dfp3.c | 31 register double f15 __asm__ ("fr15");
900 f15 = d0x;
[all...] |
