| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32r2.s | 8 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/clang/test/CodeGenCXX/ |
| aarch64-mangle-neon-vectors.cpp | 78 void f20(uint32x4_t) {} function
|
| debug-info-line.cpp | 239 void f20(int a, int b, int c) { function
|
| /external/llvm/test/MC/Mips/mips2/ |
| valid.s | 44 ceil.w.s $f6,$f20
51 cvt.w.d $f20,$f14
52 cvt.w.s $f20,$f24
54 div.d $f29,$f20,$f27
85 mov.d $f20,$f14
93 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips32/ |
| valid.s | 49 ceil.w.s $f6,$f20
58 cvt.w.d $f20,$f14
59 cvt.w.s $f20,$f24
62 div.d $f29,$f20,$f27
97 mov.d $f20,$f14
121 mul.d $f20,$f20,$f16
|
| invalid-mips32r2.s | 17 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 51 ceil.w.s $f6,$f20
62 cvt.w.d $f20,$f14
63 cvt.w.s $f20,$f24
77 div.d $f29,$f20,$f27
142 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
148 mov.d $f20,$f14
172 mul.d $f20,$f20,$f16
182 nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
185 nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38
[all...] |
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 51 ceil.w.s $f6,$f20
62 cvt.w.d $f20,$f14
63 cvt.w.s $f20,$f24
77 div.d $f29,$f20,$f27
143 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
149 mov.d $f20,$f14
173 mul.d $f20,$f20,$f16
183 nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
186 nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38
[all...] |
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 51 ceil.w.s $f6,$f20
64 cvt.w.d $f20,$f14
65 cvt.w.s $f20,$f24
82 div.d $f29,$f20,$f27
152 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
159 mov.d $f20,$f14
187 mul.d $f20,$f20,$f16
197 nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
200 nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38
[all...] |
| /external/clang/test/CodeGen/ |
| arm-arguments.c | 113 // APCS-GNU-LABEL: define void @f20(
115 // AAPCS-LABEL: define arm_aapcscc i32 @f20()
117 struct s20 f20(void) {} function
|
| x86_32-arguments-darwin.c | 98 // CHECK: void @f20(%{{.*}}* noalias sret %agg.result)
104 struct { T14 a; } f20(void) { while (1) {} } function
|
| x86_64-arguments.c | 109 // CHECK-LABEL: define void @f20(%struct.s20* byval align 32 %x)
114 void f20(struct s20 x) {} function
|
| /bionic/libc/arch-mips/bionic/ |
| setjmp.S | 155 #define SC_FPREGS_SAVED 6 /* even fp regs f20,f22,f24,f26,f28,f30 */
238 # the even-numbered double fp regs $f20,$f22,...$f30
239 s.d $f20, SC_FPREGS+0*REGSZ_FP(a0)
336 # the even-numbered double fp regs $f20,$f22,...$f30
337 l.d $f20, SC_FPREGS+0*REGSZ_FP(a0)
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 49 ceil.w.s $f6,$f20
60 cvt.w.d $f20,$f14
61 cvt.w.s $f20,$f24
66 div.d $f29,$f20,$f27
102 madd.d $f18,$f19,$f26,$f20
112 mov.d $f20,$f14
139 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 49 ceil.w.s $f6,$f20
60 cvt.w.d $f20,$f14
61 cvt.w.s $f20,$f24
66 div.d $f29,$f20,$f27
102 madd.d $f18,$f19,$f26,$f20
112 mov.d $f20,$f14
139 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 49 ceil.w.s $f6,$f20
60 cvt.w.d $f20,$f14
61 cvt.w.s $f20,$f24
66 div.d $f29,$f20,$f27
102 madd.d $f18,$f19,$f26,$f20
112 mov.d $f20,$f14
139 mul.d $f20,$f20,$f16
|
| /external/valgrind/none/tests/mips32/ |
| MoveIns.c | 303 TESTINSNMOVE("mfc1 $a3, $f20", 12, f20, a3);
332 TESTINSNMOVEt("mtc1 $a3, $f20", 14, f20, a3);
361 TESTINSNMOVE1s("mov.s $f19, $f20", 12, f19, f20);
362 TESTINSNMOVE1s("mov.s $f20, $f21", 16, f20, f21);
389 TESTINSNMOVE1d("mov.d $f18, $f20", 8, f18, f20);
[all...] |
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 47 ceil.w.s $f6,$f20
58 cvt.w.d $f20,$f14
59 cvt.w.s $f20,$f24
73 div.d $f29,$f20,$f27
140 mov.d $f20,$f14
150 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 51 ceil.w.s $f6,$f20
64 cvt.w.d $f20,$f14
65 cvt.w.s $f20,$f24
84 div.d $f29,$f20,$f27
175 mov.d $f20,$f14
203 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 51 ceil.w.s $f6,$f20
64 cvt.w.d $f20,$f14
65 cvt.w.s $f20,$f24
84 div.d $f29,$f20,$f27
175 mov.d $f20,$f14
203 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 51 ceil.w.s $f6,$f20
64 cvt.w.d $f20,$f14
65 cvt.w.s $f20,$f24
84 div.d $f29,$f20,$f27
175 mov.d $f20,$f14
203 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/ELF/ |
| cfi.s | 119 f20: label
|
| /external/llvm/test/MC/PowerPC/ |
| ppc64-regs.s | 59 #CHECK: .cfi_offset f20, 460
176 .cfi_offset f20,460
|
| /external/clang/test/Analysis/ |
| dead-stores.c | 223 void f20(void) { function
|
| /external/libunwind/src/ia64/ |
| getcontext.S | 150 stf.spill [r8] = f20, (FR(22) - FR(20)) // M2
|
